Xilinx PCI-X v5.1 manual About This Guide, Guide Contents

Page 9

R

Preface

About This Guide

The Initiator/Target v5.1 for PCI-X Getting Started Guide provides information about the LogiCORE™ IP interface core for Peripheral Component Interconnect Extended (PCI-X), which provides a fully verified, pre-implementedPCI-X bus interface targeting devices based on the Virtex™ FPGA architecture.

The guide also includes an example design in both Verilog-HDL and VHDL that lets you simulate, synthesize, and implement the interface to understand the design flow for PCI-X.

Guide Contents

This manual contains the following chapters:

•Chapter 1, “Getting Started,”describes the Initiator/Target core for PCI-X and provides information about getting technical support, and providing feedback to Xilinx about the core and the accompanying documentation.

•Chapter 2, “Licensing the Core,” provides instructions for installing and obtaining a license for the core interface, which you must do before using it in your designs.

•Chapter 3, “Family Specific Considerations,” discusses design considerations specific to the core interface targeting Virtex devices.

•Chapter 4, “Functional Simulation,” describes the use of supported functional simulation tools, including Cadence® IUS and Mentor Graphics® ModelSim®.

•Chapter 5, “Synthesizing a Design,” describes the use of supported synthesis tools, including Synplicity Synplify, Exemplar LeonardoSpectrum, and Xilinx XST.

•Chapter 6, “Implementing a Design,” describes the use of supported FPGA implementation tools, included with the Xilinx ISE™ Foundation v10.1 software.

•Chapter 7, “Timing Simulation,” describes the use of supported post-route timing simulation tools, including Cadence IUS and Mentor Graphics ModelSim.

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

9

UG158 March 24, 2008

Page 8 Page 10
Image 9
Page 8 Page 10
Contents UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-XVersion Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of FiguresPCI-X v5.1 165 Getting Started Guide About This Guide Guide ContentsTypographical ConventionsPreface About This Guide Convention Meaning or Use ExampleConventions Online DocumentPreface About This Guide Getting Started System RequirementsAbout the Example Design Technical Support Additional DocumentationFeedback Core Interface for PCI-XBefore you Begin Licensing the CoreLicensing Options Full System Hardware EvaluationFull License Installing Your License FileDirect Download Licensing the CoreDesign Support Family Specific ConsiderationsSimulation Virtex-4 Devices Wrapper Files Bus Mode Detection Configuration PinsDevice Initialization Bus Width DetectionFamily Specific Considerations Bus Clock UsageElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Cadence IUS Functional SimulationMentor Graphics ModelSim VerilogFunctional Simulation Mentor Graphics ModelSim Install Path/verilog/example/funcsimTo run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design2Main Project Window Synthesizing a Design3Files to Add Virtex Library Synplicity Synplify5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrumXilinx XST Xilinx XSTSynthesizing a Design ISE Foundation Implementing a DesignImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim
Top Page Image Contents