Xilinx PCI-X v5.1 manual Virtex-4 Devices

Page 19

Design Support

Table 3-1:Device and Interface Selection

 

 

 

 

Wrapper File

 

 

Supported Device

 

Bus Type

 

Simulation

 

Constraints File

 

 

 

 

Model

 

 

2VP40-FF1152-6C/I

 

66 MHz PCI-X

 

pcix_lc_64x

 

2vp40ff1152_64x.ucf

 

 

3.3V 64-bit

 

pcix_core

 

 

2VP40-FF1152-6C/I

 

100 MHz PCI-X

 

pcix_lc_64xf

 

2vp40ff1152_64xf.ucf

 

 

3.3V 64-bit

 

pcix_fast

 

 

2VP40-FF1152-6C/I

 

133 MHz PCI-X

 

pcix_lc_64xf

 

2vp40ff1152_64xf.ucf

 

 

3.3V 64-bit

 

pcix_fast

 

 

2VP40-FF1152-6C/I

 

33 MHz PCI

 

pcix_lc_64s

 

2vp40ff1152_64s.ucf

 

 

66 MHz PCI-X

 

pcix_core

 

 

 

 

3.3V 64-bit

 

 

 

 

2VP50-FF1152-6C/I

 

33 MHz PCI

 

pcix_lc_64n

 

2vp50ff1152_64n.ucf

 

 

3.3V 64-bit

 

pcix_core

 

 

2VP50-FF1152-6C/I

 

66 MHz PCI-X

 

pcix_lc_64x

 

2vp50ff1152_64x.ucf

 

 

3.3V 64-bit

 

pcix_core

 

 

2VP50-FF1152-6C/I

 

100 MHz PCI-X

 

pcix_lc_64xf

 

2vp50ff1152_64xf.ucf

 

 

3.3V 64-bit

 

pcix_fast

 

 

2VP50-FF1152-6C/I

 

133 MHz PCI-X

 

pcix_lc_64xf

 

2vp50ff1152_64xf.ucf

 

 

3.3V 64-bit

 

pcix_fast

 

 

2VP50-FF1152-6C/I

 

33 MHz PCI

 

pcix_lc_64s

 

2vp50ff1152_64s.ucf

 

 

66 MHz PCI-X

 

pcix_core

 

 

 

 

3.3V 64-bit

 

 

 

 

 

 

 

 

 

 

 

 

 

Virtex-4 Devices

 

 

4VFX20-FF672-10C/I

 

33 MHz PCI

 

pcix_lc_64.ng

 

4vfx20ff672_64ng.ucf

 

 

 

 

 

3.3V 64-bit

 

pcix_core

 

 

4VFX20-FF672-10C/I

 

66 MHz PCI-X

 

pcix_lc_64x

 

4vfx20ff672_64x.ucf

 

 

3.3V 64-bit

 

pcix_core

 

 

4VFX20-FF672-10C/I

 

100 MHz PCI-X

 

pcix_lc_64x

 

4vfx20ff672_64xf.ucf

 

 

3.3V 64-bit

 

pcix_core

 

 

4VFX20-FF672-10C/I

 

133 MHz PCI-X

 

pcix_lc_64x

 

4vfx20ff672_64xf.ucf

 

 

3.3V 64-bit

 

pcix_core

 

 

4VLX25-FF668-10C/I

 

33 MHz PCI

 

pcix_lc_64.ng

 

4vlx25ff668_64ng.ucf

 

 

3.3V 64-bit

 

pcix_core

 

 

4VLX25-FF668-10C/I

 

66 MHz PCI-X

 

pcix_lc_64x

 

4vlx25ff668_64x.ucf

 

 

3.3V 64-bit

 

pcix_core

 

 

 

 

 

 

 

 

 

R

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

19

UG158 March 24, 2008

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Contents UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-XVersion Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of FiguresPCI-X v5.1 165 Getting Started Guide About This Guide Guide ContentsConvention Meaning or Use Example ConventionsTypographical Preface About This GuideConventions Online DocumentPreface About This Guide System Requirements Getting StartedAbout the Example Design Core Interface for PCI-X Additional DocumentationTechnical Support FeedbackFull System Hardware Evaluation Licensing the CoreBefore you Begin Licensing OptionsLicensing the Core Installing Your License FileFull License Direct DownloadDesign Support Family Specific ConsiderationsSimulation Virtex-4 Devices Wrapper Files Bus Width Detection Configuration PinsBus Mode Detection Device InitializationFamily Specific Considerations Bus Clock UsageElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Cadence IUS Functional SimulationVerilog Mentor Graphics ModelSimFunctional Simulation Mentor Graphics ModelSim Install Path/verilog/example/funcsimTo run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design2Main Project Window Synthesizing a Design3Files to Add Virtex Library Synplicity Synplify5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrumXilinx XST Xilinx XSTSynthesizing a Design ISE Foundation Implementing a DesignImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim
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