Xilinx PCI-X v5.1 manual Version Revision

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	Version	Revision

10/10/07	9.5	Updated for IP2 Jade Minor release. Added section regarding configuration pins to
		device family chapter.

3/24/08	10.0	Updated tools for IP0K release.

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

UG158 March 24, 2008

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Contents LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24PCI-X v5.1 165 Getting Started Guide UG158 March 24 Version RevisionUg000preface.fm to Guide Version Revision Table of Contents Implementing a Design Schedule of Figures 8Options for Implementation Options/ConstraintsPCI-X v5.1 165 Getting Started Guide Guide Contents About This GuideConventions TypographicalPreface About This Guide Convention Meaning or Use ExampleOnline Document ConventionsPreface About This Guide System Requirements Getting StartedAbout the Example Design Additional Documentation Technical SupportFeedback Core Interface for PCI-XLicensing the Core Before you BeginLicensing Options Full System Hardware EvaluationInstalling Your License File Full LicenseDirect Download Licensing the CoreFamily Specific Considerations Design SupportSimulation Virtex-4 Devices Wrapper Files Configuration Pins Bus Mode DetectionDevice Initialization Bus Width DetectionBus Clock Usage Family Specific ConsiderationsElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Functional Simulation Cadence IUSVerilog Mentor Graphics ModelSimFunctional Simulation Install Path/verilog/example/funcsim Mentor Graphics ModelSimTo run the simulation, type the following do modelsim.do Synthesizing a Design Synplicity SynplifySynthesizing a Design 2Main Project WindowSynplicity Synplify 3Files to Add Virtex Library5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window Exemplar LeonardoSpectrum 15Options for Implementation DeviceXilinx XST Xilinx XSTSynthesizing a Design Implementing a Design ISE FoundationImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim