Xilinx PCI-X v5.1 Additional Documentation, Technical Support, Feedback, Core Interface for PCI-X

Page 14

R

Chapter 1: Getting Started

Step-by-step instructions using supported design tools are provided in this guide to simulate, synthesize, and implement the Userapp example design.

Additional Documentation

For more information about the core interface, see the following documents, provided in the CORE Generator zip file:

•Initiator/Target v5.1 for PCI-X User Guide

•Initiator/Target v5.1 Release Notes

Further information is available in the Mindshare PCI System Architecture text, and the PCI Local Bus Specification, available from the PCI Special Interest Group site.

Technical Support

For technical support, visit www.xilinx.com/support. Questions are routed to a team of engineers with expertise using the Initiator/Target core for PCI-X.

Xilinx provides technical support for use of this product as described in the User and Getting Started Guides for this core. Xilinx cannot guarantee timing, functionality, or support of this product for designs outside of these guidelines.

Feedback

Xilinx welcomes comments and suggestions about the core interface for PCI-X and the documentation supplied with the core.

Core Interface for PCI-X

For comments or suggestions about the core interface for PCI-X, please submit a WebCase from www.xilinx.com/support/clearexpress/websupport.htmt. Be sure to include the following information:

•Product name

•Core version number

•Explanation of your comments

Document

For comments or suggestions about this document, please submit a WebCase from www.xilinx.com/support/clearexpress/websupport.htm. Be sure to include the following information:

•Document title and number

•Page number(s) to which your comments refer

•Explanation of your comments

14	www.xilinx.com	PCI-X v5.1 165 Getting Started Guide
		UG158 March 24, 2008

Image 14

Contents LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24PCI-X v5.1 165 Getting Started Guide UG158 March 24 Version RevisionUg000preface.fm to Guide Version Revision Table of Contents Implementing a Design Schedule of Figures 8Options for Implementation Options/ConstraintsPCI-X v5.1 165 Getting Started Guide Guide Contents About This GuidePreface About This Guide ConventionsTypographical Convention Meaning or Use ExampleOnline Document ConventionsPreface About This Guide About the Example Design Getting StartedSystem Requirements Feedback Additional DocumentationTechnical Support Core Interface for PCI-XLicensing Options Licensing the CoreBefore you Begin Full System Hardware EvaluationDirect Download Installing Your License FileFull License Licensing the CoreFamily Specific Considerations Design SupportSimulation Virtex-4 Devices Wrapper Files Device Initialization Configuration PinsBus Mode Detection Bus Width DetectionBus Clock Usage Family Specific ConsiderationsElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Functional Simulation Cadence IUSFunctional Simulation Mentor Graphics ModelSimVerilog Install Path/verilog/example/funcsim Mentor Graphics ModelSimTo run the simulation, type the following do modelsim.do Synthesizing a Design Synplicity SynplifySynthesizing a Design 2Main Project WindowSynplicity Synplify 3Files to Add Virtex Library5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window Exemplar LeonardoSpectrum 15Options for Implementation DeviceXilinx XST Xilinx XSTSynthesizing a Design Implementing a Design ISE FoundationImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim