Xilinx PCI-X v5.1 manual Licensing the Core, Before you Begin, Licensing Options

Page 15

R

Chapter 2

Licensing the Core

This chapter provides instructions for installing and obtaining a license for the Initiator/Target core for PCI-X, which you must do before using it in your designs. The core is provided under the terms of the Xilinx LogiCORE Site License Agreement, which conforms to the terms of the SignOnce IP License standard defined by the Common License Consortium. Purchase of the core entitles you to technical support and access to updates for a period of one year.

This chapter assumes that you have installed the core using either the CORE Generator™ IP Software Update installer, or by performing a manual installation after downloading the core from the web. For information about installing the core, see the product lounge at PCI/PCI-X.

Before you Begin

Before installing the core, you must have a Xilinx.com account and the ISE 10.1 software installed on your system.

To create an account, and download ISE software:

1.Click Login at the top of the Xilinx home page; then follow the onscreen instructions to create a support account.

2.Install ISE software v10.1 and the applicable service pack software. ISE service packs can be downloaded from www.xilinx.com/support/download.htm.

Licensing Options

The PCI-X core provides two licensing options, described in this section.

Full System Hardware Evaluation

The Full System Hardware Evaluation license is available at no cost and lets you fully integrate the core into an FPGA design, place and route the design, evaluate timing, and perform back-annotated gate-level simulation of the core using the demonstration test bench provided.

In addition, the license lets you generate a bitstream from the placed and routed design, which can then be downloaded to a supported device and tested in hardware. The core can be tested in the target device for a limited time before timing out (ceasing to function) at which time it can be reactivated by reconfiguring the device.

You can obtain a Full System Evaluation license for this core by contacting your local Xilinx FAE to request a Full System Hardware Evaluation license key.

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

15

UG158 March 24, 2008

Page 14 Page 16
Image 15
Page 14 Page 16
Contents UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-XVersion Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of FiguresPCI-X v5.1 165 Getting Started Guide About This Guide Guide ContentsConvention Meaning or Use Example ConventionsTypographical Preface About This GuideConventions Online DocumentPreface About This Guide Getting Started System RequirementsAbout the Example Design Core Interface for PCI-X Additional DocumentationTechnical Support FeedbackFull System Hardware Evaluation Licensing the CoreBefore you Begin Licensing OptionsLicensing the Core Installing Your License FileFull License Direct DownloadDesign Support Family Specific ConsiderationsSimulation Virtex-4 Devices Wrapper Files Bus Width Detection Configuration PinsBus Mode Detection Device InitializationFamily Specific Considerations Bus Clock UsageElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Cadence IUS Functional SimulationMentor Graphics ModelSim VerilogFunctional Simulation Mentor Graphics ModelSim Install Path/verilog/example/funcsimTo run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design2Main Project Window Synthesizing a Design3Files to Add Virtex Library Synplicity Synplify5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrumXilinx XST Xilinx XSTSynthesizing a Design ISE Foundation Implementing a DesignImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim
Top Page Image Contents