Mitel MT90840 manual Serial Data Memory Addressing

Page 18

MT90840

Preliminary Information

all 16 serial streams can be individually controlled, so that up to 512 channels can be either transmitted or received. As an example, if all DC bit locations of RPCM High are set HIGH, all 512 channels on STo0-7 and STi0-7 will be configured as outputs. If all DC bits are LOW, then all 512 channels will be configured as inputs. In Add/Drop mode all 512 serial channels are copied into the Transmit Path Data Memory, as inputs, regardless of the DC or OE bits. This has the effect of a “copy-back” of all serial outputs.

For more details on per-channel control functions for the serial and parallel data ports, see the TPCM High and RPCM High bits definition in the Register Description section.

Serial Data Memory Addressing

The serial port mode determines the number of channels per stream, the number of streams, and the direction-control operation. Therefore the way in which serial data is addressed in the internal memory space must change with the serial port mode. Because of this, it is necessary to select the serial port mode (with DR1-0 and FDC in the IMS register) before programming the Receive Path Connection Memory.

2.048 Mbps Balanced Mode

The 2.048 Mbps Balanced mode has 8 serial input and 8 serial output streams, and 32 channels per stream. Therefore 3 bits are used to address the 8 streams, and 5 bits are used to address the 32 channels. Figure 11a shows how the Transmit Path Data Memory is read in this mode, by the CPU, or by the Transmit Path Connection Memory. Each of the 256 input channels is mapped to an address in the TPDM. CPU reads require the LSB (Least Significant Bit) of the CAR Register, and the 7 LSBs of the address bus. The source-channel address-value written in the TPCM requires 8 bits.

Figure 11b shows how the Receive Path Connection Memory is addressed by the CPU. Each of the 256 output channels has a control-address in the RPCM. CPU accesses require the LSB of the CAR Register, and the 7 LSBs of the address bus. When the DC bit for a specific output channel is LOW, that channel is output on the STi pin rather than the STo pin, and the data at the STo pin is input to the TPDM. When the DC bit is HIGH, the output channel appears at the normal STo pin.

 

 

Serial Input

TPDM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Channel

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU Port Addressing:

 

 

 

 

 

 

 

STi0, Ch0

 

000H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CAR

 

Address Bus

 

 

 

 

 

 

 

STi0, Ch1

 

001H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

 

0

 

 

6

5

4

3

2

1

 

0

 

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Stream

 

 

Channel

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STi7, Ch30

0FEH

 

TPCM Contents:

 

 

 

 

 

 

 

 

 

 

 

0FFH

 

 

 

 

 

 

 

 

 

 

STi7, Ch31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

6

5

 

 

4

3

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: Only 256

memory

 

Stream

 

 

Channel

 

 

 

 

 

 

 

 

Bits 7:5 select one of 8 streams.

 

 

 

locations.

 

 

 

 

 

 

 

 

 

 

 

Bits 4:0 select one of 32

 

 

 

 

 

 

 

 

channels per stream.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 11a - 2.048 Mbps Balanced Mode TPDM

 

 

 

 

Addressing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial Output

RPCM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Channel

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STo0, Ch0

 

000H

 

CPU Port Addressing:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STo0, Ch1

 

001H

CAR

 

Address Bus

 

 

 

 

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

 

0

 

 

6

5

4

3

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STo7, Ch30

0FEH

 

 

 

Stream

 

 

Channel

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0FFH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STo7, Ch31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: Only 256 memory locations.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 11b - 2.048 Mbps Balanced Mode RPCM

Addressing

2.048 Mbps Add/Drop Mode

The 2.048 Mbps Add/Drop mode has 16 serial input/ output streams, and 32 channels per stream. Therefore 4 bits are used to address the 16 streams, and 5 bits are used to address the 32 channels. Figure 12a shows how the Transmit Path Data Memory is read in this mode. Each of the 512 possible input channels is mapped to an address in the TPDM. CPU reads require the 2 LSBs of the CAR Register, and the 7 LSBs of the address bus. The source-channel address-value written in the TPCM requires 9 bits. In this mode the TPDM reads all 512 serial channels as inputs. When a specific channel is driven by the MT90840 as an output, the output data is also copied back into the TPDM.

Figure 12b shows how the Receive Path Connection Memory is addressed by the CPU in 2.048 Mbps Add/Drop mode. Each of the 512 possible output channels has a control-address in the RPCM. CPU accesses require the 2 LSBs of the CAR Register, and the 7 LSBs of the address bus. When the DC bit or the OE bit at a specific control-address is LOW, no data is driven out for that channel, and the input data at the pin is written to the TPDM.

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Contents Features ApplicationsPIN Plcc Pin ConnectionsDescription 100 Pin DescriptionPin # No ConnectionPckr PcktTDI +5 Volt Power Supply GroundTime Slot Interchange Operation Switching Functional DescriptionDevice Operation PPFRi PDi0-7 C4/8R1&2 4 MHz Serial I/O 2 MbpsSerial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Bypass/Parallel-Switching Path Transmit PathReceive Path Serial Data Port Parallel Port Clock Signals and Framing Serial Frame PulseParallel Data Port Timing Mode 1 TM1 Ring Master Timing and Switching ControlOutput Driver Enable Control Capability Asynchronous Parallel Port With ST-BUS Clock MasterTiming Mode 2 TM2 Ring Slave TM1 Multiple-MT90840 Sub-Mode PfdiAsynchronous Parallel Port With ST-BUS Clock Slave External PLL and C4 Phase-Correction Internal 4.096 MHz Clock DividerTM2 Multiple-MT90840 Sub-Mode Sfdi Synchronous Parallel Port With ST-BUS Clock Slave Sfdi =Sfdi = MT90840 Per-channel Bypass on the Parallel Port MT90840 Throughput DelayMT90840 Per-channel Functions Per-channel Control Outputs on the Parallel PortMode Data Rates Minimum Delay Total Throughput Delay MT90840 Throughput Delay SummaryPer-channel Tri-state Serial and Parallel Per-channel Message Mode Serial and ParallelSTi0 STo0 Per-channel Direction Control on the Serial PortSerial Data Memory Addressing Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing IRQ Interrupt Pin Microprocessor PortAddress Mapping of the Internal Registers DTA Data Transfer Acknowledgment PinAccessing Internal Memories HexMT90840 Register Address Mapping Detecting Clock Presence Clock Quality and TM1 Tpcm Access IntegrityClock Quality and TM2 Rpcm Access Integrity Memory Block-ProgrammingTiming Mode Initialization Jtag SupportI01 Instruction Description Test Access Port TAPBoundary-Scan Instruction Register Boundary-Scan Instruction RegisterBoundary-Scan Register Cells Definitions Test Data RegistersCells Definition HighRegister Description Interface Mode Selection Register IMS READ/WRITETiming Mode Register TIM READ/WRITE DR1General Purpose Mode Register GPM READ/WRITE Alarm Status Register ALS READ/WRITEPhase Status Registers PSD Read Only Control Register CR READ/WRITEInternal Memory Description AB9 AB8AB11 AB10 Distributed Isochronous Network CTI Distributed Architecture Implemented with the MT90840Characteristics Sym Min Typ‡ Max Units Test Conditions/Pins Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ Max Units Test Conditions Absolute Maximum RatingsCharacteristics Sym Min Typ‡ Max Units Test Conditions TM1Characteristics Sym Min Typ‡ Units Test ConditionsOutput Pin Test Point Serial Port with Negative Polarity F0 ST-BUS Serial Port with Positive Polarity F0 GCISerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Negative Polarity Spfp = F0 Frame Sync with Positive Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Positive Polarity Spfp = Frame Sync with Negative Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 AC Electrical Characteristics Parallel Data Port Parallel Port Receive TimingParallel Port in Timing Mode RD/WR 774 Up to 3 C4 cycles + Register takd-wrIntel/National Multiplexed Bus Timing AD0AC Electrical Characteristics† Motorola Multiplexed Bus Mode Characteristics Sym MinAD0-7 AD0-13Parameter Symbol Min Max Units Test Conditions Boundary Scan Test Port TimingDimensions in inches are not exact Dim Min MaxNot to scale 280

MT90840 specifications

The Mitel MT90840 is an advanced telecommunications device designed to enhance connectivity and communication capabilities for various applications. With its robust array of features and technologies, the MT90840 is well-suited for businesses looking to improve their communications infrastructure.

One of the standout features of the Mitel MT90840 is its integration of voice and data services. This allows users to manage their communications more efficiently, streamlining operations and reducing costs. The device supports a wide range of voice codecs, ensuring high-quality audio during calls and providing flexibility for users who may require different standards for different applications.

Another key characteristic of the MT90840 is its scalability. The device is designed to grow with the needs of a business. It supports multiple lines and can be configured to handle an increasing number of users without compromising performance. This scalability is particularly advantageous for organizations that may undergo growth or changes in their communication needs over time.

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Additionally, the MT90840 is designed with user-friendliness in mind. It features an intuitive interface that simplifies operation, making it accessible even for those who may not be tech-savvy. The device is compatible with various peripherals, such as headsets and conferencing equipment, further enhancing its usability in diverse settings, from small offices to large conference rooms.

Moreover, the Mitel MT90840 offers excellent interoperability with a variety of third-party applications. This flexibility enables organizations to integrate the device into their existing systems seamlessly, thereby enhancing productivity without requiring a complete technological overhaul.

In conclusion, the Mitel MT90840 stands out as a versatile and reliable telecommunications solution. Its rich feature set, including voice and data integration, scalability, VoIP capabilities, user-friendly interface, and interoperability, makes it an ideal choice for businesses looking to elevate their communications strategy.
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