Mitel manual Synchronous Parallel Port With ST-BUS Clock Slave, Sfdi = MT90840

Timing Mode 3 (TM3) - Bus Slave

Synchronous Parallel Port With ST-BUS Clock Slave

Timing Mode 3 is used where the main TDM clock ref- erence resides on the parallel port side of the system, and where the receive parallel port and the transmit parallel port are aligned. (An example is a node on a backplane.) Timing on the serial port is tightly tied to the receive parallel port, and the transmit parallel port is clocked by the receive parallel port clock. In TM3, PCKT and PPFTo are not used. See Figure 7 for a connection example.

In TM3, the MT90840 timing is controlled by the parallel port frame pulse (PPFRi) and clock (PCKR).

The MT90840 generates the serial port output frame pulse (F0o) locked to PPFRi. TM3 is similar to TM2 with two main differences: the parallel Bypass Path is disabled, and the parallel port receive and transmit buses are synchronized and both aligned with PPFRi. A fixed offset exists between F0o and PPFRi due to serial-to-parallel conversion. The MT90840 will align F0o so that it proceeds PPFRi by 3.8 μsec.

In TM3 the internal clock divider circuit is always enabled, regardless of the state of the INTCLK bit (C4/8R1 and C4/8R2 are unused). Therefore TM3 is limited to 19.44 and 16.384 Mbyte/s parallel port rates, and 2.048 and 4.096 Mbps serial port rates.