Mitel MT90840 manual Parallel Port in Timing Mode

Page 43
TCP = 0
TCP = 1

Preliminary Information

MT90840

PCKR

PPFRi

PPFT

tdf

tdf

PPFT

Note: For the PPFT depicted above, PPFP = HIGH. If PPFP is LOW, the PPFT line will have negative pulse polarity.

Figure 29 - Parallel Port in Timing Mode 4

STo (4 Mbps)

Ch. 3 Bit 1

 

Ch. 3 Bit 0 (4 Mbps)

 

 

 

 

 

 

 

Ch. 4 Bit 7

 

C4/8R1 or C4/8R2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(ST-BUS Mode)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tpv

tpv

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCKT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PPFTo

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PDo7-0

 

 

 

 

 

 

 

 

 

 

 

n-2

n-1

n

0

 

1

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: The MT90840 will correct phase relation in TM1 by moving PPFTo (by moving F0o in TM2 andTM3).

 

 

Figure 30 - Phase Variation Between C4/8R1 & C4/8R2 and PCKT Inputs for TM1 Operation

STo (4 Mbps)

Ch. 61 Bit 2

 

Ch. 61 Bit 1 (4 Mbps)

Ch. 61 Bit 0

SPCKo

 

 

 

 

 

(ST-BUS Mode)

 

 

 

 

 

 

 

 

tpv

tpv

 

PCKR

 

 

 

 

 

PPFRi

 

 

 

 

 

PDi7-0

n-1

n

0

1

2

 

 

 

 

 

Note: The MT90840 will correct phase relation in TM2 by inverting SPCKo w.r.t. C4/8R1 or C4/8R2.

Figure 31 - Phase Variation Between C4 and PCKR Inputs for TM2 Operation

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Contents
Applications FeaturesPin Connections PIN PlccNo Connection Pin DescriptionPin # Description 100Pckt PckrTDI Ground +5 Volt Power SupplyFunctional Description Time Slot Interchange Operation SwitchingDevice Operation Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7 C4/8R1&2 4 MHz Serial I/O 2 MbpsSerial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps PPFRi PDi0-7Transmit Path Bypass/Parallel-Switching PathReceive Path Serial Data Port Serial Frame Pulse Parallel Port Clock Signals and FramingParallel Data Port Asynchronous Parallel Port With ST-BUS Clock Master Timing and Switching ControlOutput Driver Enable Control Capability Timing Mode 1 TM1 Ring MasterTM1 Multiple-MT90840 Sub-Mode Pfdi Timing Mode 2 TM2 Ring SlaveAsynchronous Parallel Port With ST-BUS Clock Slave Internal 4.096 MHz Clock Divider External PLL and C4 Phase-CorrectionTM2 Multiple-MT90840 Sub-Mode Sfdi Sfdi = Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 Per-channel Control Outputs on the Parallel Port MT90840 Throughput DelayMT90840 Per-channel Functions Per-channel Bypass on the Parallel PortMT90840 Throughput Delay Summary Mode Data Rates Minimum Delay Total Throughput DelayPer-channel Direction Control on the Serial Port Per-channel Message Mode Serial and ParallelSTi0 STo0 Per-channel Tri-state Serial and ParallelAddressing Serial Data Memory Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing DTA Data Transfer Acknowledgment Pin Microprocessor PortAddress Mapping of the Internal Registers IRQ Interrupt PinHex Accessing Internal MemoriesMT90840 Register Address Mapping Memory Block-Programming Clock Quality and TM1 Tpcm Access IntegrityClock Quality and TM2 Rpcm Access Integrity Detecting Clock PresenceJtag Support Timing Mode InitializationBoundary-Scan Instruction Register Test Access Port TAPBoundary-Scan Instruction Register I01 Instruction DescriptionHigh Test Data RegistersCells Definition Boundary-Scan Register Cells DefinitionsDR1 Interface Mode Selection Register IMS READ/WRITETiming Mode Register TIM READ/WRITE Register DescriptionAlarm Status Register ALS READ/WRITE General Purpose Mode Register GPM READ/WRITEControl Register CR READ/WRITE Phase Status Registers PSD Read OnlyAB9 AB8 Internal Memory DescriptionAB11 AB10 CTI Distributed Architecture Implemented with the MT90840 Distributed Isochronous NetworkAbsolute Maximum Ratings Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ Max Units Test Conditions Characteristics Sym Min Typ‡ Max Units Test Conditions/PinsTM1 Characteristics Sym Min Typ‡ Max Units Test ConditionsUnits Test Conditions Characteristics Sym Min Typ‡Output Pin Test Point Serial Port with Positive Polarity F0 GCI Serial Port with Negative Polarity F0 ST-BUSSerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Positive Polarity Spfp = F0 Frame Sync with Negative Polarity Spfp = Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Negative Polarity Spfp = Frame Sync with Positive Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 Parallel Port Receive Timing AC Electrical Characteristics Parallel Data PortParallel Port in Timing Mode 774 Up to 3 C4 cycles + Register takd-wr RD/WRAD0 Intel/National Multiplexed Bus TimingCharacteristics Sym Min AC Electrical Characteristics† Motorola Multiplexed Bus ModeAD0-13 AD0-7Boundary Scan Test Port Timing Parameter Symbol Min Max Units Test ConditionsDim Min Max Dimensions in inches are not exactNot to scale 280
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