Mitel MT90840 Serial Frame Pulse, Parallel Data Port, Parallel Port Clock Signals and Framing

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MT90840

Preliminary Information

Register enables the internal divider, and the SPCKo output (and internal 4.096 MHz clocks) are driven by the clock divided-down from PCKR. At 16.384 MHz, this is a simple divide-by-4, and the SPCKo output jitter will depend on the PCKR input jitter. At 19.44 MHz, the SPCKo output jitter will be larger as the divider switches between rising and falling edges of PCKR. The serial port timing and F0o frame pulse are tightly slaved to PPFRi when INTCLK is set high.

Serial Frame Pulse

In TM1, the MT90840 receives the frame reference (F0i) from an external source, and the MT90840 senses the polarity of the frame pulse and adapts the device timing to the appropriate (ST-BUS or GCI) format.

In TM2 and TM3, the MT90840 outputs the serial port frame pulse (F0o). Positive (GCI) or negative (ST-BUS) frame pulse formats, and the associated clock polarity, can be selected for the F0o signal by programming the SPFP bit in the GPM Register. This flexibility allows the MT90840 to be employed with different serial bus formats.

In applications which require a large number of serial channels in TM2, it is possible to operate multiple MT90840s in parallel using the SFDI control bit (in the TIM register). To allow the MT90840s to synchronize their internal timing, all of the MT90840s are connected to the same C4/8 reference source, and one MT90840 in normal TM2 (SFDI set low) supplies F0 to one or more MT90840s in TM2 with SFDI set high. With SFDI set high, F0 becomes an input, and this allows the MT90840 driving F0 to control the timing of one or more other MT90840s. If the internal 4.096 MHz clock divider is used (INTCLK high) it is not necessary to use the SFDI control, as the serial port timing and F0o frame pulse of each parallel MT90840 will be tightly slaved to PPFRi when INTCLK is set high.

Should the input framing at F0i cease while the C4/8 clock continues to run, the MT90840 will continue to function as if the frame pulse was asserted after the normal number of clock cycles (free run). If F0i re-commences the MT90840 will immediately sync to F0i, but changes in the F0i interval will temporarily disrupt the TDM data streams. If the F0i input is held asserted, the serial I/O will “lock up” and operation will be disrupted.

Parallel Data Port

The MT90840 parallel port is composed of an 8-bit wide Parallel Data Output Port (PDo0-7), a 4-bit wide Control output port (CTo0-3), an 8-bit wide Parallel

Data Input Port (PDi0-7), a Receive Frame sync signal (PPFRi) and a Transmit Frame sync signal (PPFT), and Transmit (PCKT) and Receive (PCKR) Clocks.

The Parallel Port Rates are controlled by the PPS bits in the IMS register, and are:

•19.44 Mbyte/s (2430 channels),

•16.384 Mbyte/s (2048 channels), and

•6.48 Mbyte/s (810 channels).

The user can further specify the features of the parallel TDM port, including:

•the edge of the parallel port clock used to transmit data and PPFTo (see TCP bit in the TIM register),

•the polarity of the Parallel Port Frame Transmit pulse PPFT (see PPFP bit in the GPM register),

•the use of PPFT (normally an output) as an input in TM1, if the application requires multiple MT90840 devices to operate in parallel (see PFDI bit in the TIM register).

The parallel port of the MT90840 is flexible enough to interface to a variety of applications. It can be connected to a framer to access a serial transport backbone running at up to 155 Mbps. It can be connected to a backplane-type parallel bus. It can share a parallel bus with other devices, using the control outputs (CTo0-3) and the per-channel tristate function to share access to the bus.

Parallel Port Clock Signals and Framing

The MT90840's PPFRi (Parallel Port Frame pulse Receive input) and PPFTi/o (Parallel Port Frame pulse Transmit i/o) signals synchronize the MT90840 to the high speed data frame. Receive data is clocked in at the Parallel Data inputs (PDi0-7) by the Parallel port Receive ClocK (PCKR), as framed by Receive Parallel Port Frame input (PPFRi). In TM2, TM3 and TM4, PCKR also clocks the Parallel Data outputs (PDo0-7), with the framing in TM2 and TM4 indicated by the PPFTo output. In TM1, the Parallel Data outputs are clocked out by PCKT, with the framing indicated by PPFTo. Alternatively, the Transmit framing can be controlled by the PPFTi input if the PFDI bit in the TIM register has been set high, to enable multiple MT90840s to operate in parallel in TM1.

Should the input framing at PPFRi cease while the PCKR clock continues to run, the MT90840 will continue to function as if the frame pulse was asserted after the normal number of clock cycles (free run). If PPFRi re-commences, the MT90840 will immediately sync to PPFRi, but any change in the framing interval will temporarily disrupt the TDM data

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Contents Features ApplicationsPIN Plcc Pin ConnectionsDescription 100 Pin DescriptionPin # No ConnectionPckt PckrTDI +5 Volt Power Supply GroundFunctional Description Time Slot Interchange Operation SwitchingDevice Operation PPFRi PDi0-7 C4/8R1&2 4 MHz Serial I/O 2 MbpsSerial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Transmit Path Bypass/Parallel-Switching PathReceive Path Serial Data Port Serial Frame Pulse Parallel Port Clock Signals and FramingParallel Data Port Timing Mode 1 TM1 Ring Master Timing and Switching ControlOutput Driver Enable Control Capability Asynchronous Parallel Port With ST-BUS Clock MasterTM1 Multiple-MT90840 Sub-Mode Pfdi Timing Mode 2 TM2 Ring SlaveAsynchronous Parallel Port With ST-BUS Clock Slave Internal 4.096 MHz Clock Divider External PLL and C4 Phase-CorrectionTM2 Multiple-MT90840 Sub-Mode Sfdi Sfdi = Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 Per-channel Bypass on the Parallel Port MT90840 Throughput DelayMT90840 Per-channel Functions Per-channel Control Outputs on the Parallel PortMode Data Rates Minimum Delay Total Throughput Delay MT90840 Throughput Delay SummaryPer-channel Tri-state Serial and Parallel Per-channel Message Mode Serial and ParallelSTi0 STo0 Per-channel Direction Control on the Serial PortSerial Data Memory Addressing Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing IRQ Interrupt Pin Microprocessor PortAddress Mapping of the Internal Registers DTA Data Transfer Acknowledgment PinHex Accessing Internal MemoriesMT90840 Register Address Mapping Detecting Clock Presence Clock Quality and TM1 Tpcm Access IntegrityClock Quality and TM2 Rpcm Access Integrity Memory Block-ProgrammingTiming Mode Initialization Jtag SupportI01 Instruction Description Test Access Port TAPBoundary-Scan Instruction Register Boundary-Scan Instruction RegisterBoundary-Scan Register Cells Definitions Test Data RegistersCells Definition HighRegister Description Interface Mode Selection Register IMS READ/WRITETiming Mode Register TIM READ/WRITE DR1General Purpose Mode Register GPM READ/WRITE Alarm Status Register ALS READ/WRITEPhase Status Registers PSD Read Only Control Register CR READ/WRITEInternal Memory Description AB9 AB8AB11 AB10 Distributed Isochronous Network CTI Distributed Architecture Implemented with the MT90840Characteristics Sym Min Typ‡ Max Units Test Conditions/Pins Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ Max Units Test Conditions Absolute Maximum RatingsCharacteristics Sym Min Typ‡ Max Units Test Conditions TM1Units Test Conditions Characteristics Sym Min Typ‡Output Pin Test Point Serial Port with Negative Polarity F0 ST-BUS Serial Port with Positive Polarity F0 GCISerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Negative Polarity Spfp = F0 Frame Sync with Positive Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Positive Polarity Spfp = Frame Sync with Negative Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 AC Electrical Characteristics Parallel Data Port Parallel Port Receive TimingParallel Port in Timing Mode RD/WR 774 Up to 3 C4 cycles + Register takd-wrIntel/National Multiplexed Bus Timing AD0AC Electrical Characteristics† Motorola Multiplexed Bus Mode Characteristics Sym MinAD0-7 AD0-13Parameter Symbol Min Max Units Test Conditions Boundary Scan Test Port TimingDim Min Max Dimensions in inches are not exactNot to scale 280

MT90840 specifications

The Mitel MT90840 is an advanced telecommunications device designed to enhance connectivity and communication capabilities for various applications. With its robust array of features and technologies, the MT90840 is well-suited for businesses looking to improve their communications infrastructure.

One of the standout features of the Mitel MT90840 is its integration of voice and data services. This allows users to manage their communications more efficiently, streamlining operations and reducing costs. The device supports a wide range of voice codecs, ensuring high-quality audio during calls and providing flexibility for users who may require different standards for different applications.

Another key characteristic of the MT90840 is its scalability. The device is designed to grow with the needs of a business. It supports multiple lines and can be configured to handle an increasing number of users without compromising performance. This scalability is particularly advantageous for organizations that may undergo growth or changes in their communication needs over time.

The Mitel MT90840 also incorporates advanced networking technologies, such as VoIP (Voice over Internet Protocol). This allows users to make voice calls using the internet rather than traditional phone lines, reducing costs for long-distance calls and improving overall communication efficiency. The device is equipped with features that support secure, encrypted communication, further protecting sensitive data and conversations from potential breaches.

Additionally, the MT90840 is designed with user-friendliness in mind. It features an intuitive interface that simplifies operation, making it accessible even for those who may not be tech-savvy. The device is compatible with various peripherals, such as headsets and conferencing equipment, further enhancing its usability in diverse settings, from small offices to large conference rooms.

Moreover, the Mitel MT90840 offers excellent interoperability with a variety of third-party applications. This flexibility enables organizations to integrate the device into their existing systems seamlessly, thereby enhancing productivity without requiring a complete technological overhaul.

In conclusion, the Mitel MT90840 stands out as a versatile and reliable telecommunications solution. Its rich feature set, including voice and data integration, scalability, VoIP capabilities, user-friendly interface, and interoperability, makes it an ideal choice for businesses looking to elevate their communications strategy.
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