Mitel MT90840 manual Ground, +5 Volt Power Supply

Page 5

Preliminary Information

MT90840

Pin Description (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin #

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

Description

 

 

 

 

84

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

59

10

 

 

 

 

 

 

 

Test Reset (Input). Asynchronously initializes the JTAG TAP controller, placing it

 

 

TRST

 

 

 

 

 

 

 

 

 

in the Test-Logic-Resetstate. This pin is pulled high internally when not driven.

 

 

 

 

 

 

 

 

 

 

This pin should be pulsed low on power-up, or held low continuously, to ensure

 

 

 

 

 

 

 

 

 

 

that the MT90840 is in the normal functional state, and not the test state.

 

 

 

 

 

 

 

 

60

11

 

 

TCK

Test Clock (Input). Provides the clock to the JTAG test logic. This pin is pulled high

 

 

 

 

 

 

 

 

 

 

by an internal pull-up when not driven.

 

 

 

 

 

 

 

 

 

 

 

61

12

 

 

TMS

Test Mode Select (Input). JTAG signal that controls the state transitions of the

 

 

 

 

 

 

 

 

 

 

TAP controller, sampled on rising TCK. This pin is pulled high by an internal

 

 

 

 

 

 

 

 

 

 

pull-up when not driven.

 

 

 

 

 

 

 

 

 

 

 

62

13

 

 

TDO

Test Data (Output). JTAG serial data is output on this pin on the falling edge of

 

 

 

 

 

 

 

 

 

 

TCK. This pin is held in a high impedance state when JTAG scan is not enabled.

 

 

 

 

 

 

65

16

SPCKo

Serial Port Clock (Output) In TM2 and TM3, this is a 4.096 MHz clock output

 

 

 

 

 

 

 

 

 

 

derived from the system 4.096 MHz reference. (As controlled by the C4/8R bit and

 

 

 

 

 

 

 

 

 

 

the INTCLK bit in the TIM Register.) This output is used to shift data in and out of

 

 

 

 

 

 

 

 

 

 

the serial port.

 

 

 

 

 

 

 

 

 

 

 

 

 

In TM1 and TM4, this output is automatically placed in high impedance.

 

 

 

 

 

 

 

 

 

 

For applications with the serial port running at 8.192 Mbps this output is not used,

 

 

 

 

 

 

 

 

 

 

and an 8.192 MHz clock source must be supplied at C4/8R1 or C4/8R2.

 

 

 

 

 

 

66-73

17-24

STo7-STo0

Serial Output Streams 7 to 0 (Bidirectional). Serial TDM data-streams at 2.048,

 

 

 

 

 

 

 

 

 

 

4.096 or 8.192 Mbps, with 32, 64 or 128 channels respectively per stream. For

 

 

 

 

 

 

 

 

 

 

2.048 and 4.096 Mbps applications, streams STo0-STo7 can be used, while for

 

 

 

 

 

 

 

 

 

 

8.192 Mbps, only streams STo0-STo3 are used (512 channel limit). These eight

 

 

 

 

 

 

 

 

 

 

bidirectional lines can be programmed as inputs or outputs (default) on a

 

 

 

 

 

 

 

 

 

 

per-channel basis.

 

 

 

 

 

 

 

 

 

76-83

32-39

AD0-AD7

Multiplexed Address/Data Bus (Bidirectional). These I/O lines provide an 8-bit

 

 

 

 

 

 

 

 

 

 

interface to a microprocessor for control and monitoring of the MT90840. These

 

 

 

 

 

 

 

 

 

 

pins function as eight input address lines to the Address Latch circuit as well as

 

 

 

 

 

 

 

 

 

 

eight data I/O lines.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

84

40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

\ WR

Read/Write \ Write (Input). In Motorola multiplexed-bus mode this input is

 

 

 

 

 

 

 

 

 

 

R/W, which controls the direction of the data bus lines (AD0-AD7) during a

 

 

 

 

 

 

 

 

 

 

microprocessor access. In Intel/National multiplexed-bus mode this input is

WR,

 

 

 

 

 

 

 

 

 

 

 

an active low signal which configures the data bus lines (AD0-AD7) as inputs

 

 

 

 

 

 

 

 

 

 

during a microprocessor write access.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1,11

15,25,

 

 

VSS

Ground.

 

 

 

 

24,32,

41,55,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

43,53,

68,74,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64,74

90,10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2, 12,

5, 14,

 

 

VDD

+5 Volt Power Supply.

 

 

 

 

25,33

26,42

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

44,54,

56,69,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63,75

75,91

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2-235

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Page 4 Page 6
Contents
Applications FeaturesPin Connections PIN PlccPin # Pin DescriptionDescription 100 No ConnectionTDI PckrPckt Ground +5 Volt Power SupplyDevice Operation Time Slot Interchange Operation SwitchingFunctional Description Serial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps C4/8R1&2 4 MHz Serial I/O 2 MbpsPPFRi PDi0-7 Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Receive Path Bypass/Parallel-Switching PathTransmit Path Serial Data Port Parallel Data Port Parallel Port Clock Signals and FramingSerial Frame Pulse Output Driver Enable Control Capability Timing and Switching ControlTiming Mode 1 TM1 Ring Master Asynchronous Parallel Port With ST-BUS Clock MasterAsynchronous Parallel Port With ST-BUS Clock Slave Timing Mode 2 TM2 Ring SlaveTM1 Multiple-MT90840 Sub-Mode Pfdi TM2 Multiple-MT90840 Sub-Mode Sfdi External PLL and C4 Phase-CorrectionInternal 4.096 MHz Clock Divider Sfdi = MT90840 Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 Per-channel Functions MT90840 Throughput DelayPer-channel Bypass on the Parallel Port Per-channel Control Outputs on the Parallel PortMT90840 Throughput Delay Summary Mode Data Rates Minimum Delay Total Throughput DelaySTi0 STo0 Per-channel Message Mode Serial and ParallelPer-channel Tri-state Serial and Parallel Per-channel Direction Control on the Serial PortAddressing Serial Data Memory Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing Address Mapping of the Internal Registers Microprocessor PortIRQ Interrupt Pin DTA Data Transfer Acknowledgment PinMT90840 Register Address Mapping Accessing Internal MemoriesHex Clock Quality and TM2 Rpcm Access Integrity Clock Quality and TM1 Tpcm Access IntegrityDetecting Clock Presence Memory Block-ProgrammingJtag Support Timing Mode InitializationBoundary-Scan Instruction Register Test Access Port TAPI01 Instruction Description Boundary-Scan Instruction RegisterCells Definition Test Data RegistersBoundary-Scan Register Cells Definitions HighTiming Mode Register TIM READ/WRITE Interface Mode Selection Register IMS READ/WRITERegister Description DR1Alarm Status Register ALS READ/WRITE General Purpose Mode Register GPM READ/WRITEControl Register CR READ/WRITE Phase Status Registers PSD Read OnlyAB9 AB8 Internal Memory DescriptionAB11 AB10 CTI Distributed Architecture Implemented with the MT90840 Distributed Isochronous NetworkCharacteristics Sym Min Typ Max Units Test Conditions Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ‡ Max Units Test Conditions/Pins Absolute Maximum RatingsTM1 Characteristics Sym Min Typ‡ Max Units Test ConditionsOutput Pin Test Point Characteristics Sym Min Typ‡Units Test Conditions Serial Port with Positive Polarity F0 GCI Serial Port with Negative Polarity F0 ST-BUSSerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Positive Polarity Spfp = F0 Frame Sync with Negative Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Negative Polarity Spfp = Frame Sync with Positive Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 Parallel Port Receive Timing AC Electrical Characteristics Parallel Data PortParallel Port in Timing Mode 774 Up to 3 C4 cycles + Register takd-wr RD/WRAD0 Intel/National Multiplexed Bus TimingCharacteristics Sym Min AC Electrical Characteristics† Motorola Multiplexed Bus ModeAD0-13 AD0-7Boundary Scan Test Port Timing Parameter Symbol Min Max Units Test ConditionsNot to scale Dimensions in inches are not exactDim Min Max 280
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