Mitel MT90840 manual Timing for the Parallel Port External Control Lines CTo0-3

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Preliminary Information

MT90840

PCKT/PCKR

PDo0-7

CTo0-3

PCKT/PCKR

byte m-1

PDo0-7

tcdf

CTo0-3

 

 

 

 

 

 

 

 

 

TCP controls the clock-edge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

on which the output changes.

byte m-1

 

 

 

byte m

byte m+1

tcdf

 

 

 

 

 

 

 

 

TCP = 1

 

 

 

 

CTo corresponding to

 

 

 

 

 

 

 

CTo corresponding to

 

 

 

 

 

byte m

byte m+1

 

 

 

 

 

 

 

 

 

 

byte mbyte m+1

TCP = 0

CTo corresponding to

CTo corresponding to

byte m

byte m+1

Figure 25 - Timing for the Parallel Port External Control Lines CTo0-3

 

 

 

tclk

 

 

 

 

 

tclkh

tclkl

 

PCKT

 

 

 

 

 

 

 

tza

tsod

 

taz

 

 

 

 

PDo0-7

tristate

byte n

byte 0

byte 1

tristate

 

 

 

 

 

n = 2429, 2047, or 809

PPFTi (PPFP=1)

 

tPPFS

tPPFH

 

 

 

 

 

Figure 26 - TM1 Parallel Port Transmit Timing (TM1 & PFDI = 1, PPFT is an input)

PCKT/PCKR

PDo0-7 tristate

PPFTo (PPFP=1)

 

tclk

 

 

tclkh

tclkl

tza

tsod

 

byte n

byte 0

 

 

tdf

 

 

tdf

 

byte 1

tdf

tdf

taz

tristate

PPFTo (PPFP=0)

Note: The depicted output timing occurs when TCP = 0. If TCP = 1, the byte at PDo0-7 port and the PPFT line will be output on the falling edge of the PCKT/PCKR clock.

Figure 27 - Parallel Port Transmit Timing (PFDI = 0, PPFT is an output)

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Contents
Applications FeaturesPin Connections PIN PlccPin # Pin DescriptionDescription 100 No ConnectionTDI PckrPckt Ground +5 Volt Power SupplyDevice Operation Time Slot Interchange Operation SwitchingFunctional Description Serial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps C4/8R1&2 4 MHz Serial I/O 2 MbpsPPFRi PDi0-7 Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Receive Path Bypass/Parallel-Switching PathTransmit Path Serial Data Port Parallel Data Port Parallel Port Clock Signals and FramingSerial Frame Pulse Output Driver Enable Control Capability Timing and Switching ControlTiming Mode 1 TM1 Ring Master Asynchronous Parallel Port With ST-BUS Clock MasterAsynchronous Parallel Port With ST-BUS Clock Slave Timing Mode 2 TM2 Ring SlaveTM1 Multiple-MT90840 Sub-Mode Pfdi TM2 Multiple-MT90840 Sub-Mode Sfdi External PLL and C4 Phase-CorrectionInternal 4.096 MHz Clock Divider Sfdi = MT90840 Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 Per-channel Functions MT90840 Throughput DelayPer-channel Bypass on the Parallel Port Per-channel Control Outputs on the Parallel PortMT90840 Throughput Delay Summary Mode Data Rates Minimum Delay Total Throughput DelaySTi0 STo0 Per-channel Message Mode Serial and ParallelPer-channel Tri-state Serial and Parallel Per-channel Direction Control on the Serial PortAddressing Serial Data Memory Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing Address Mapping of the Internal Registers Microprocessor PortIRQ Interrupt Pin DTA Data Transfer Acknowledgment PinMT90840 Register Address Mapping Accessing Internal MemoriesHex Clock Quality and TM2 Rpcm Access Integrity Clock Quality and TM1 Tpcm Access IntegrityDetecting Clock Presence Memory Block-ProgrammingJtag Support Timing Mode InitializationBoundary-Scan Instruction Register Test Access Port TAPI01 Instruction Description Boundary-Scan Instruction RegisterCells Definition Test Data RegistersBoundary-Scan Register Cells Definitions HighTiming Mode Register TIM READ/WRITE Interface Mode Selection Register IMS READ/WRITERegister Description DR1Alarm Status Register ALS READ/WRITE General Purpose Mode Register GPM READ/WRITEControl Register CR READ/WRITE Phase Status Registers PSD Read OnlyAB9 AB8 Internal Memory DescriptionAB11 AB10 CTI Distributed Architecture Implemented with the MT90840 Distributed Isochronous NetworkCharacteristics Sym Min Typ Max Units Test Conditions Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ‡ Max Units Test Conditions/Pins Absolute Maximum RatingsTM1 Characteristics Sym Min Typ‡ Max Units Test ConditionsOutput Pin Test Point Characteristics Sym Min Typ‡Units Test Conditions Serial Port with Positive Polarity F0 GCI Serial Port with Negative Polarity F0 ST-BUSSerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Positive Polarity Spfp = F0 Frame Sync with Negative Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Negative Polarity Spfp = Frame Sync with Positive Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 Parallel Port Receive Timing AC Electrical Characteristics Parallel Data PortParallel Port in Timing Mode 774 Up to 3 C4 cycles + Register takd-wr RD/WRAD0 Intel/National Multiplexed Bus TimingCharacteristics Sym Min AC Electrical Characteristics† Motorola Multiplexed Bus ModeAD0-13 AD0-7Boundary Scan Test Port Timing Parameter Symbol Min Max Units Test ConditionsNot to scale Dimensions in inches are not exactDim Min Max 280
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