Mitel MT90840 General Purpose Mode Register GPM READ/WRITE, Alarm Status Register ALS READ/WRITE

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Preliminary Information

MT90840

 

 

 

 

General Purpose Mode Register (GPM) - READ/WRITE

 

BPD7 BPD6 BPD5

BPD4 PPFP

DIN

SPFP

BPE

7

6

5

4

3

2

1

0

BPD7-4Block-Programming Data bits 7-4. These bits carry the value to be loaded into the TPCM-High or RPCM-High memory when the Memory Block-Programming feature is activated. When BPE is set HIGH, the contents of bits BPD7-4 are loaded into the four most significant bits of TPCM-High or RPCM-High, and the four least significant bits of TPCM-High or RPCM-High are zeroed.

PPFP Parallel Port Frame pulse Polarity. Used to program the polarity of the PPFT frame pulse. If PPFP is set HIGH, the frame boundaries at the Parallel Port output will occur when PPFT pulse signal is HIGH. If PPFP is set LOW, the PPFT output will indicate frame boundaries with a LOW active pulse. The transmit edge for the generation of PPFT, as well as PDo and CTo, is determined by TCP in the TIM Register.

DIN Device Initialization. This bit is used in TM1 and TM2 to center the phase relation between the parallel port clocks and the serial port clock. It can be set HIGH by the CPU after the serial and parallel port rates are written in the IMS Register, and the input clocks are stable. If the MT90840 internal divider is used (INTCLK bit = HIGH), or if TM4 or TM3 is selected, this bit is not used. This bit is automatically returned low after 8 frames, and clears all interrupt source bits in the ALS register as long as it is HIGH. The Connect Memories should not be programmed while DIN is asserted.

SPFP Serial Port Framing Polarity. In TM2 and TM3 this bit defines the format of the serial port frame pulse F0o, and the clock SPCKo. If SPFP is HIGH, F0o is set as a positive pulse with GCI timing. If SPFP is LOW, F0o is set as a negative pulse with ST-BUS timing. In TM2 with SFDI set HIGH, this bit specifies the expected F0i input polarity. In TM1, the F0i input polarity is automatically detected, and this bit is ignored. See the interface timing specifications.

BPE Block-Programming Enable. This bit activates the memory block-programming feature. It can be set high after the SEL0-2 bits in the Control Register are set to select the memory to be programmed. The BPE and BPD7-4 bits in this register must be defined in the same write operation. Once BPE is set HIGH, the user should wait at least 250 μs and then check BPE = LOW to see that the operation completed successfully. This bit can also be written low to force the end of the block-program operation.

Note: The CPU must maintain the required settings of the PPFP and SPFP bits when BPE is written. The DIN function and the BPE function should not be used simultaneously.

Alarm Status Register (ALS) - READ/WRITE

MSK3 MSK2 MSK1 MSK0 PPCE RXPAA TXPAA FSA

7

6

5

4

3

2

1

0

MSK3-0Mask Alarm Bits 3-0. These bits mask the specific interrupt source bits. MSK3 masks PPCE, MSK2 masks RXPAA, etc. If MSKn is set HIGH, the corresponding interrupt source is enabled, and the IRQ pin will respond to that interrupt source; if set LOW, the corresponding interrupt source is masked. When masked, an interrupt source will not assert the IRQ pin, but will still set the ALS register bit. On system power-up, all interrupts are masked. Writes to the ALS register clear the low nibble (interrupt source bits) regardless of the data written.

PPCE Parallel Port Frame Counter Error. Used in all timing modes. The PPCE bit goes HIGH whenever there is an incorrect number of PCKR clock cycles between PPFRi frame sync signals on the Receive parallel port. The numbers of clock cycles expected depends on the parallel port rate selected in the IMS Register (2430, 2048, or 810 clock cycles). The absence of PPFRi for one or more frames will not cause an interrupt (allowing free-run operation), but the PPCE bit will go HIGH if PPFRi occurs anywhere but on an expected frame boundary.

RXPAA RX Phase Alignment Alarm. Used in TM2 operation, when INTCLK = 0. The RXPAA bit goes HIGH whenever the C4/8 input reference goes out of phase relative to the parallel port clock (PCKR). A rising edge on the RXPAA bit indicates that the MT90840 has adjusted the position of F0o and SPCKo, and a data slip at the serial port has occurred. Note that a CPU write to the RPCM memory as RXPAA goes HIGH (in TM2) may be corrupted. In TM2 with SFDI = 1, a rising edge on the RXPAA bit indicates that the F0i input is out of phase with PPFRi, implying a failure in the timing supplied by the controlling (TM2 with SFDI = 0) MT90840. When not in TM2 the RXPAA bit may be continuously asserted, and therefore should be masked by setting MSK2 LOW, and ignored.

TXPAA TX Phase Alignment Alarm. Used in TM1 operation. The TXPAA bit goes HIGH whenever the PCKT clock input goes out of phase relative to the C4/8 clock. A rising edge on the TXPAA bit indicates that the MT90840 has adjusted the position of PPFTo, and a data slip at the TX parallel port output has occurred. Note that a CPU write to the TPCM memory as TXPAA goes HIGH (in TM1) may be corrupted. In TM1 with PFDI = 1, a rising edge on the TXPAA bit indicates that the PPFTi input is out of phase with F0i, implying a failure in the timing supplied by the controlling (TM1 with PFDI=0) MT90840.

FSA Frame Slip on Elastic Buffer. Used in TM1 operation. The FSA bit goes HIGH when either an overflow or underun condition on the Receive parallel port’s elastic buffer has been detected. A rising edge on the FSA bit indicates that a frame of data from the RX parallel port has been dropped, or repeated. In TM2, TM3, and TM4 the user should mask this bit by setting MSK0 LOW.

Note: The interrupt source bits are latched, and remain high until cleared by the CPU. The interrupt source bits (ALS low nibble) are cleared by writing the mask bits (ALS high nibble), regardless of the data written.

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Contents Applications FeaturesPin Connections PIN PlccNo Connection Pin DescriptionPin # Description 100Pckr PcktTDI Ground +5 Volt Power SupplyTime Slot Interchange Operation Switching Functional DescriptionDevice Operation Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7 C4/8R1&2 4 MHz Serial I/O 2 MbpsSerial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps PPFRi PDi0-7Bypass/Parallel-Switching Path Transmit PathReceive Path Serial Data Port Parallel Port Clock Signals and Framing Serial Frame PulseParallel Data Port Asynchronous Parallel Port With ST-BUS Clock Master Timing and Switching ControlOutput Driver Enable Control Capability Timing Mode 1 TM1 Ring MasterTiming Mode 2 TM2 Ring Slave TM1 Multiple-MT90840 Sub-Mode PfdiAsynchronous Parallel Port With ST-BUS Clock Slave External PLL and C4 Phase-Correction Internal 4.096 MHz Clock DividerTM2 Multiple-MT90840 Sub-Mode Sfdi Synchronous Parallel Port With ST-BUS Clock Slave Sfdi =Sfdi = MT90840 Per-channel Control Outputs on the Parallel Port MT90840 Throughput DelayMT90840 Per-channel Functions Per-channel Bypass on the Parallel PortMT90840 Throughput Delay Summary Mode Data Rates Minimum Delay Total Throughput DelayPer-channel Direction Control on the Serial Port Per-channel Message Mode Serial and ParallelSTi0 STo0 Per-channel Tri-state Serial and ParallelAddressing Serial Data Memory Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing DTA Data Transfer Acknowledgment Pin Microprocessor PortAddress Mapping of the Internal Registers IRQ Interrupt PinAccessing Internal Memories HexMT90840 Register Address Mapping Memory Block-Programming Clock Quality and TM1 Tpcm Access IntegrityClock Quality and TM2 Rpcm Access Integrity Detecting Clock PresenceJtag Support Timing Mode InitializationBoundary-Scan Instruction Register Test Access Port TAPBoundary-Scan Instruction Register I01 Instruction DescriptionHigh Test Data RegistersCells Definition Boundary-Scan Register Cells DefinitionsDR1 Interface Mode Selection Register IMS READ/WRITETiming Mode Register TIM READ/WRITE Register DescriptionAlarm Status Register ALS READ/WRITE General Purpose Mode Register GPM READ/WRITEControl Register CR READ/WRITE Phase Status Registers PSD Read OnlyAB9 AB8 Internal Memory DescriptionAB11 AB10 CTI Distributed Architecture Implemented with the MT90840 Distributed Isochronous NetworkAbsolute Maximum Ratings Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ Max Units Test Conditions Characteristics Sym Min Typ‡ Max Units Test Conditions/PinsTM1 Characteristics Sym Min Typ‡ Max Units Test ConditionsCharacteristics Sym Min Typ‡ Units Test ConditionsOutput Pin Test Point Serial Port with Positive Polarity F0 GCI Serial Port with Negative Polarity F0 ST-BUSSerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Positive Polarity Spfp = F0 Frame Sync with Negative Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Negative Polarity Spfp = Frame Sync with Positive Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 Parallel Port Receive Timing AC Electrical Characteristics Parallel Data PortParallel Port in Timing Mode 774 Up to 3 C4 cycles + Register takd-wr RD/WRAD0 Intel/National Multiplexed Bus TimingCharacteristics Sym Min AC Electrical Characteristics† Motorola Multiplexed Bus ModeAD0-13 AD0-7Boundary Scan Test Port Timing Parameter Symbol Min Max Units Test ConditionsDimensions in inches are not exact Dim Min MaxNot to scale 280

MT90840 specifications

The Mitel MT90840 is an advanced telecommunications device designed to enhance connectivity and communication capabilities for various applications. With its robust array of features and technologies, the MT90840 is well-suited for businesses looking to improve their communications infrastructure.

One of the standout features of the Mitel MT90840 is its integration of voice and data services. This allows users to manage their communications more efficiently, streamlining operations and reducing costs. The device supports a wide range of voice codecs, ensuring high-quality audio during calls and providing flexibility for users who may require different standards for different applications.

Another key characteristic of the MT90840 is its scalability. The device is designed to grow with the needs of a business. It supports multiple lines and can be configured to handle an increasing number of users without compromising performance. This scalability is particularly advantageous for organizations that may undergo growth or changes in their communication needs over time.

The Mitel MT90840 also incorporates advanced networking technologies, such as VoIP (Voice over Internet Protocol). This allows users to make voice calls using the internet rather than traditional phone lines, reducing costs for long-distance calls and improving overall communication efficiency. The device is equipped with features that support secure, encrypted communication, further protecting sensitive data and conversations from potential breaches.

Additionally, the MT90840 is designed with user-friendliness in mind. It features an intuitive interface that simplifies operation, making it accessible even for those who may not be tech-savvy. The device is compatible with various peripherals, such as headsets and conferencing equipment, further enhancing its usability in diverse settings, from small offices to large conference rooms.

Moreover, the Mitel MT90840 offers excellent interoperability with a variety of third-party applications. This flexibility enables organizations to integrate the device into their existing systems seamlessly, thereby enhancing productivity without requiring a complete technological overhaul.

In conclusion, the Mitel MT90840 stands out as a versatile and reliable telecommunications solution. Its rich feature set, including voice and data integration, scalability, VoIP capabilities, user-friendly interface, and interoperability, makes it an ideal choice for businesses looking to elevate their communications strategy.
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