Mitel MT90840 manual STi0 STo0, Per-channel Tri-state Serial and Parallel

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Preliminary Information

MT90840

 

PPFT

 

 

PDo7-0

 

 

 

Channel 2428

Byte Timing

 

CTo0-3

 

 

 

 

 

 

TPCM High, CTn bit

Outputs

 

address 2428

Output Frame Boundary Established by PPFT

Channel 2429

Channel 0

Channel 1

 

 

 

 

 

 

TPCM High, CTn bit

TPCM High, CTn bit

TPCM High, CTn bit

address 2429

address 0

address 1

 

 

 

Note: For applications at 16.384 and 6.48 Mbyte/s, only 2048 and 810 positions are usable, in the TPCM.

Figure 9 - Parallel Port Control Outputs, CTo0-3

 

 

 

 

DC=0 for STo 0 channel 1

 

 

 

 

 

 

 

 

O/P

 

STi0

I/P

 

 

 

 

I/P

 

STo0

O/P

 

 

0

1

2

. . . . .

29

30

31

MT90840

1

2

3

. . . . .

29

30

31

3

0

 

 

 

 

 

 

 

 

DC=1 for STo 0 channel 29

 

 

 

 

 

 

 

Figure 10 - Balanced Per-Channel Serial Direction Control as Determined by DC Bit

TPCM High location is output on the corresponding CTo pin once every frame. See Figure 9. The control outputs can be used to control other devices, such as buffers, to allow sharing of the parallel port data bus.

Per-channel Tri-state (Serial and Parallel)

The MT90840 provides per-channel tri-state of the output pins on both the serial and parallel port. The OE bit in each address of the TPCM and RPCM determines if data will be driven during a particular time slot, or if the pin will be placed in a high-impedance state during that time slot. The OE bit overrides all other per-channel control bits.

Per-channel Message Mode (Serial and Parallel)

The MT90840 provides per-channel message mode capability on both the serial and parallel port. The MC bit in each address of the TPCM and RPCM determines if the Connection Memory Low byte is to be used as an address, or as data to be output on the particular channel (message mode). When the MC bit is HIGH, the Connection Memory Low byte is used as message data. As well as driving message data on the serial (RPCM) and parallel (TPCM) ports, the MT90840 allows the CPU to read serial or parallel data channels from the TPDM or RPDM. Applications for message mode include digital silence, proprietary signalling, and creating fixed 8 kHz framing patterns.

Per-channel Direction Control on the Serial Port

The MT90840 provides the ability to use any nominal output serial channel as an input or as an output. The direction of each output serial channel is controlled by the DC bit in the appropriate byte of the Receive Path Connection Memory High (RPCM High). When DC is HIGH the matching channel is an output. The per-channel direction control feature of the MT90840 can be activated in one two modes: balanced, or add/drop operation.

Balanced Operation (all serial data rates)

This mode is enabled when the FDC bit in the IMS Register is LOW. In this mode, each of the DC bits controls two serial channels: the nominal output and the nominal input. If a channel on a nominal output serial stream (STo0-7) is re-defined as an input, the same-number channel on the matching input stream (STi0-7) will be defined as an output. For example, if channel 0 on STo7 is programmed as an input (DC=0), then channel 0 on STi7 is defined as an output. Each DC-bit’s state controls the direction of a channel on the nominal output stream (DC is HIGH for output), and inverse-sense controls a channel on the nominal input stream (DC is LOW for output). This is shown in Figure 10.

Add/Drop Operation (2.048 Mbps only)

This mode is enabled when the FDC bit in the IMS Register is HIGH. In Add/Drop mode all channels on

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Contents Applications FeaturesPin Connections PIN PlccPin # Pin DescriptionDescription 100 No ConnectionTDI PckrPckt Ground +5 Volt Power SupplyDevice Operation Time Slot Interchange Operation SwitchingFunctional Description Serial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps C4/8R1&2 4 MHz Serial I/O 2 MbpsPPFRi PDi0-7 Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Receive Path Bypass/Parallel-Switching PathTransmit Path Serial Data Port Parallel Data Port Parallel Port Clock Signals and FramingSerial Frame Pulse Output Driver Enable Control Capability Timing and Switching ControlTiming Mode 1 TM1 Ring Master Asynchronous Parallel Port With ST-BUS Clock MasterAsynchronous Parallel Port With ST-BUS Clock Slave Timing Mode 2 TM2 Ring SlaveTM1 Multiple-MT90840 Sub-Mode Pfdi TM2 Multiple-MT90840 Sub-Mode Sfdi External PLL and C4 Phase-CorrectionInternal 4.096 MHz Clock Divider Sfdi = MT90840 Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 Per-channel Functions MT90840 Throughput DelayPer-channel Bypass on the Parallel Port Per-channel Control Outputs on the Parallel PortMT90840 Throughput Delay Summary Mode Data Rates Minimum Delay Total Throughput DelaySTi0 STo0 Per-channel Message Mode Serial and ParallelPer-channel Tri-state Serial and Parallel Per-channel Direction Control on the Serial PortAddressing Serial Data Memory Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing Address Mapping of the Internal Registers Microprocessor PortIRQ Interrupt Pin DTA Data Transfer Acknowledgment PinMT90840 Register Address Mapping Accessing Internal MemoriesHex Clock Quality and TM2 Rpcm Access Integrity Clock Quality and TM1 Tpcm Access IntegrityDetecting Clock Presence Memory Block-ProgrammingJtag Support Timing Mode InitializationBoundary-Scan Instruction Register Test Access Port TAPI01 Instruction Description Boundary-Scan Instruction RegisterCells Definition Test Data RegistersBoundary-Scan Register Cells Definitions HighTiming Mode Register TIM READ/WRITE Interface Mode Selection Register IMS READ/WRITERegister Description DR1Alarm Status Register ALS READ/WRITE General Purpose Mode Register GPM READ/WRITEControl Register CR READ/WRITE Phase Status Registers PSD Read OnlyAB9 AB8 Internal Memory DescriptionAB11 AB10 CTI Distributed Architecture Implemented with the MT90840 Distributed Isochronous NetworkCharacteristics Sym Min Typ Max Units Test Conditions Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ‡ Max Units Test Conditions/Pins Absolute Maximum RatingsTM1 Characteristics Sym Min Typ‡ Max Units Test ConditionsOutput Pin Test Point Characteristics Sym Min Typ‡Units Test Conditions Serial Port with Positive Polarity F0 GCI Serial Port with Negative Polarity F0 ST-BUSSerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Positive Polarity Spfp = F0 Frame Sync with Negative Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Negative Polarity Spfp = Frame Sync with Positive Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 Parallel Port Receive Timing AC Electrical Characteristics Parallel Data PortParallel Port in Timing Mode 774 Up to 3 C4 cycles + Register takd-wr RD/WRAD0 Intel/National Multiplexed Bus TimingCharacteristics Sym Min AC Electrical Characteristics† Motorola Multiplexed Bus ModeAD0-13 AD0-7Boundary Scan Test Port Timing Parameter Symbol Min Max Units Test ConditionsNot to scale Dimensions in inches are not exactDim Min Max 280

MT90840 specifications

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