Mitel MT90840 manual Test Data Registers, Boundary-Scan Register Cells Definitions, High

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Preliminary Information

MT90840

Test Data Registers

As specified in the IEEE 1149.1 Standard, the MT90840 JTAG interface contains two test data registers:

•The Boundary Scan Register consists of a series of Boundary-Scan Cells arranged to form a scan path around the boundary of the core logic of the MT90840.

•The Bypass Register is a single stage shift-register that provides a one-bit path that minimizes the distance for test data shifting from the MT90840’s TDI to its TDO.

The MT90840 Boundary-Scan register contains 107 bits. The suffix (‘in’, ‘out’, or ‘en’) indicates the nature and direction of the BSC. Bit 1 in Table 4 is the first bit clocked out. All tristate enable bits are asserted HIGH (i.e. a logic 1 enables the corresponding group of output/bidirectional pins). Note that clocking all zeros into the scan path register will set all outputs to tristate (outputs disabled).

Cells

 

 

Definition

Note

 

 

 

 

1

 

ppfri_in

first bit

 

 

 

 

 

out

 

 

 

 

2

 

pckt_in

 

 

 

 

 

3

 

pckr_in

 

 

 

 

 

4:11

 

pdi<0:7>_in

 

 

 

 

 

12:14

 

ppft_en, ppft_out, ppft_in

 

 

 

 

 

15:22

 

pdo<0:7>_out

 

 

 

 

 

23

 

pdo_en

enables

 

 

 

 

 

pdo<0:7

 

 

 

 

 

>outputs

 

 

 

 

24:27

 

cto<0:3>_out

always

 

 

 

 

 

enabled

 

 

 

 

28

 

c48r2_in

 

 

 

 

 

 

 

29:31

 

 

 

 

 

f0_en, f0_out, f0_in

 

 

 

 

 

32

 

c48r1_in

 

 

 

 

 

33:35

 

sti<7>_en, sti<7>_out,

 

 

 

sti<7>_in

 

 

 

 

 

36:53

 

sti<6>, sti<5>, ... sti<1>

 

 

 

 

 

54:56

 

sti<0>_en, sti<0>_out,

 

 

 

sti<0>_in

 

 

 

 

 

 

57

 

 

 

 

res_in

 

Table 4 - Boundary-Scan Register

Cells

 

 

 

Definitions

 

Note

 

 

 

 

 

 

58

 

irq_en

tied

 

 

 

 

 

 

HIGH

 

 

 

 

 

 

internally

 

 

 

 

 

 

 

 

 

 

 

59

 

irq_out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60

 

 

 

_out

‘pseudo’

 

dta

 

 

 

 

 

 

open-dra

 

 

 

 

 

 

in

 

 

 

 

 

 

 

 

 

 

 

 

61

 

 

_in

 

 

 

 

 

 

 

cs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

62

 

asale_in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63

 

dsrdb_in

 

 

 

 

 

 

 

pin: ds/rd

 

 

 

 

 

 

64

 

wrb_in

pin:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

r/w\wr

 

 

 

 

 

 

 

 

 

 

 

65:66

 

ad<7>_out, ad<7>_in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

67:78

 

ad<6>, ad<5>, ... ad<1>

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

79:80

 

ad<0>_out, ad<0>_in

 

 

 

 

 

 

 

 

 

 

 

 

81

 

ad_en

enables

 

 

 

 

 

 

ad<0:7>

 

 

 

 

 

 

outputs

 

 

 

 

 

 

 

 

 

 

 

82:84

 

sto<0>_en, sto<0>_out,

 

 

 

 

 

 

 

 

 

sto<0>_in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

85:102

 

sto<1>, sto<2>, ... sto<6>

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

103:105

 

sto<7>_en, sto<7>_out,

 

 

 

 

 

 

 

 

 

sto<7>_in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

106:107

 

spcko_en, spcko_out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4 - Boundary Scan Register

Please visit our web site at www.semicon.mitel.com to download a BSDL file for the MT90840.

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Contents
Applications FeaturesPin Connections PIN PlccPin # Pin DescriptionDescription 100 No ConnectionPckt PckrTDI Ground +5 Volt Power SupplyFunctional Description Time Slot Interchange Operation SwitchingDevice Operation Serial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps C4/8R1&2 4 MHz Serial I/O 2 MbpsPPFRi PDi0-7 Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Transmit Path Bypass/Parallel-Switching PathReceive Path Serial Data Port Serial Frame Pulse Parallel Port Clock Signals and FramingParallel Data Port Output Driver Enable Control Capability Timing and Switching ControlTiming Mode 1 TM1 Ring Master Asynchronous Parallel Port With ST-BUS Clock MasterTM1 Multiple-MT90840 Sub-Mode Pfdi Timing Mode 2 TM2 Ring SlaveAsynchronous Parallel Port With ST-BUS Clock Slave Internal 4.096 MHz Clock Divider External PLL and C4 Phase-CorrectionTM2 Multiple-MT90840 Sub-Mode Sfdi Sfdi = Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 MT90840 Per-channel Functions MT90840 Throughput DelayPer-channel Bypass on the Parallel Port Per-channel Control Outputs on the Parallel PortMT90840 Throughput Delay Summary Mode Data Rates Minimum Delay Total Throughput DelaySTi0 STo0 Per-channel Message Mode Serial and ParallelPer-channel Tri-state Serial and Parallel Per-channel Direction Control on the Serial PortAddressing Serial Data Memory Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing Address Mapping of the Internal Registers Microprocessor PortIRQ Interrupt Pin DTA Data Transfer Acknowledgment Pin Hex Accessing Internal Memories MT90840 Register Address Mapping Clock Quality and TM2 Rpcm Access Integrity Clock Quality and TM1 Tpcm Access IntegrityDetecting Clock Presence Memory Block-ProgrammingJtag Support Timing Mode InitializationBoundary-Scan Instruction Register Test Access Port TAPI01 Instruction Description Boundary-Scan Instruction RegisterCells Definition Test Data RegistersBoundary-Scan Register Cells Definitions HighTiming Mode Register TIM READ/WRITE Interface Mode Selection Register IMS READ/WRITERegister Description DR1Alarm Status Register ALS READ/WRITE General Purpose Mode Register GPM READ/WRITEControl Register CR READ/WRITE Phase Status Registers PSD Read OnlyAB9 AB8 Internal Memory DescriptionAB11 AB10 CTI Distributed Architecture Implemented with the MT90840 Distributed Isochronous NetworkCharacteristics Sym Min Typ Max Units Test Conditions Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ‡ Max Units Test Conditions/Pins Absolute Maximum RatingsTM1 Characteristics Sym Min Typ‡ Max Units Test ConditionsUnits Test Conditions Characteristics Sym Min Typ‡Output Pin Test Point Serial Port with Positive Polarity F0 GCI Serial Port with Negative Polarity F0 ST-BUSSerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Positive Polarity Spfp = F0 Frame Sync with Negative Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Negative Polarity Spfp = Frame Sync with Positive Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 Parallel Port Receive Timing AC Electrical Characteristics Parallel Data PortParallel Port in Timing Mode 774 Up to 3 C4 cycles + Register takd-wr RD/WRAD0 Intel/National Multiplexed Bus TimingCharacteristics Sym Min AC Electrical Characteristics† Motorola Multiplexed Bus ModeAD0-13 AD0-7Boundary Scan Test Port Timing Parameter Symbol Min Max Units Test ConditionsDim Min Max Dimensions in inches are not exactNot to scale 280
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