Mitel manual MT90840 Throughput Delay, MT90840 Per-channel Functions

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Preliminary Information

 

 

 

 

 

 

 

MT90840

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Reference

 

 

 

 

 

 

8

 

 

MT90840

Parallel Data Out

 

 

 

 

 

 

 

 

8

 

 

 

 

 

Parallel Data In

 

PDi0-7 PDo0-7

 

 

 

 

 

 

 

 

TX 8 kHz REF

 

 

 

 

 

 

 

 

 

 

 

PPFTo

 

 

 

 

8 kHz

 

 

8 kHz RX

 

 

 

 

 

PPFRi

 

 

 

 

 

 

Source

 

 

 

 

 

 

 

 

 

 

 

 

PCKR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19.44 or 16.384 MHz (RX)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 8 - Timing Mode 4 Configuration

Timing Mode 4 (TM4) - Parallel Data Switching

Timing Mode 4 is used to provide switching of up to 2430 parallel input channels to the same number of parallel output channels. Parallel TDM data is clocked in at PDi0-7 by PCKR, framed by PPFRi. Switching is performed as programmed in the Tx Path Connection Memory, and data is output on PDo0-7, framed by PPFTo and clocked by PCKR. See Figure 8 for connection details.

In TM4, PPFTo and PDo0-7 are offset (delayed) from PPFRi and PDi0-7 by a fixed 4 clock cycles (3.5 clock cycles if the TCP bit is high). All the serial port data and timing signals, and PCKT, are unused in TM4. The internal clock divider is used to generate an internal C4 clock to allow CPU reads from the RPDM. TM4 is only available for 19.44 and 16.384 Mbyte/s rates.

MT90840 Throughput Delay

In many isochronous applications it is important to know and/or limit the delay of data. Table 1 summarizes the data throughput delay values for all timing modes of the MT90840. It is worth noting that the worst-case “round-trip” delays are not as large as the sum of the worst-case delays on the individual links. This is shown by the last 5 rows of Table 1, which give the delays for some representative two MT90840 setups.

MT90840 Per-channel Functions

Several functions of the MT90840 are programmable for each individual parallel channel or serial channel. Per-channel functions on the parallel port side are programmed in the Transmit Path Connection Memory High (TPCM High), and per-channel functions on the serial port interface are programmed in the Receive Path Connection Memory High (RPCM High). On the parallel port

these per-channel features are Bypass, Control Outputs, Output Enable, and Message Mode. On the serial port the per-channel features are Output Enable, Message Mode and Direction Control. These functions are generally available in all of the data rates and timing/switching modes.

Per-channel Bypass on the Parallel Port

This feature, when enabled, causes the specific individual parallel output channel at PDo to transmit the data received at the same number input channel at PDi. This can be used to perform a bypass (on a ring) or a loopback (in a star). This feature is only provided in Timing Modes 1 and 2. In TM2 the data-delay from PDi to PDo is fixed (as is the delay between PPFRi and PPFT). In TM1 the data-delay is elastic (and dependent on the timing of PPFRi and F0i).

The per-channel bypass feature is controlled by the PPBY bits of the TPCM High as explained in the register section. If the PPBY bit is HIGH at a specific TPCM address, the corresponding parallel output will transmit the data received in the corresponding input channel. When the PPBY bit is LOW, the corresponding output channel can be used for message-mode data, or for switched-data from the serial port. A bypass input channel is still copied to the Receive Path Data Memory, and may also be switched to the serial port, or read by the CPU from the Receive Path Data Memory.

The MT90840 per-channel output-enable and message-mode bits have higher priority than the PPBY bit.

Per-channel Control Outputs on the Parallel Port

The MT90840 provides four control outputs (CTo0-CTo3) which are synchronized to the parallel port output timing. Each of the CTo output pins is controlled by the CT0-3 bits of the TPCM High. (The CTo0 pin and bit are programmed with the Output Enable data.) The contents of the CTo bit in each

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Contents
Applications FeaturesPin Connections PIN PlccNo Connection Pin DescriptionPin # Description 100Pckr PcktTDI Ground +5 Volt Power SupplyTime Slot Interchange Operation Switching Functional DescriptionDevice Operation Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7 C4/8R1&2 4 MHz Serial I/O 2 MbpsSerial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps PPFRi PDi0-7Bypass/Parallel-Switching Path Transmit PathReceive Path Serial Data Port Parallel Port Clock Signals and Framing Serial Frame PulseParallel Data Port Asynchronous Parallel Port With ST-BUS Clock Master Timing and Switching Control Output Driver Enable Control Capability Timing Mode 1 TM1 Ring MasterTiming Mode 2 TM2 Ring Slave TM1 Multiple-MT90840 Sub-Mode PfdiAsynchronous Parallel Port With ST-BUS Clock Slave External PLL and C4 Phase-Correction Internal 4.096 MHz Clock DividerTM2 Multiple-MT90840 Sub-Mode Sfdi Synchronous Parallel Port With ST-BUS Clock Slave Sfdi =Sfdi = MT90840 Per-channel Control Outputs on the Parallel Port MT90840 Throughput DelayMT90840 Per-channel Functions Per-channel Bypass on the Parallel PortMT90840 Throughput Delay Summary Mode Data Rates Minimum Delay Total Throughput DelayPer-channel Direction Control on the Serial Port Per-channel Message Mode Serial and ParallelSTi0 STo0 Per-channel Tri-state Serial and ParallelAddressing Serial Data Memory Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing DTA Data Transfer Acknowledgment Pin Microprocessor PortAddress Mapping of the Internal Registers IRQ Interrupt PinAccessing Internal Memories HexMT90840 Register Address Mapping Memory Block-Programming Clock Quality and TM1 Tpcm Access IntegrityClock Quality and TM2 Rpcm Access Integrity Detecting Clock PresenceJtag Support Timing Mode InitializationBoundary-Scan Instruction Register Test Access Port TAPBoundary-Scan Instruction Register I01 Instruction DescriptionHigh Test Data RegistersCells Definition Boundary-Scan Register Cells DefinitionsDR1 Interface Mode Selection Register IMS READ/WRITETiming Mode Register TIM READ/WRITE Register DescriptionAlarm Status Register ALS READ/WRITE General Purpose Mode Register GPM READ/WRITEControl Register CR READ/WRITE Phase Status Registers PSD Read OnlyAB9 AB8 Internal Memory DescriptionAB11 AB10 CTI Distributed Architecture Implemented with the MT90840 Distributed Isochronous NetworkAbsolute Maximum Ratings Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ Max Units Test Conditions Characteristics Sym Min Typ‡ Max Units Test Conditions/PinsTM1 Characteristics Sym Min Typ‡ Max Units Test ConditionsCharacteristics Sym Min Typ‡ Units Test ConditionsOutput Pin Test Point Serial Port with Positive Polarity F0 GCI Serial Port with Negative Polarity F0 ST-BUSSerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Positive Polarity Spfp = F0 Frame Sync with Negative Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Negative Polarity Spfp = Frame Sync with Positive Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 Parallel Port Receive Timing AC Electrical Characteristics Parallel Data PortParallel Port in Timing Mode 774 Up to 3 C4 cycles + Register takd-wr RD/WRAD0 Intel/National Multiplexed Bus TimingCharacteristics Sym Min AC Electrical Characteristics† Motorola Multiplexed Bus ModeAD0-13 AD0-7Boundary Scan Test Port Timing Parameter Symbol Min Max Units Test ConditionsDimensions in inches are not exact Dim Min MaxNot to scale 280
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