Mitel MT90840 manual Absolute Maximum Ratings, Parameter Symbol Min Max Units

Page 32

MT90840

Preliminary Information

synchronization scheme may be used in applications such as the proposed MVIP multi-chassis level 3 interface (MC-3 system) utilizing point-to-point or point-to-multipoint switching connections.

When the MT90840 operates in a ring application, the Parallel Data Bypass mode is provided to allow

all or part of the received input parallel data to be bypassed to the output parallel port feeding the ring back with the data which is not destined for the local station. The data destined for the local station can be dropped through CPU programming. In this mode, the CPU has full control of the outgoing bandwidth (from the serial interface to the high speed link) so that it does not contend with the bypassed data.

Absolute Maximum Ratings*

 

Parameter

Symbol

Min

Max

Units

 

 

 

 

 

 

1

Supply Voltage

VDD

0

6

V

2

Voltage on any I/O pin

VI

VSS-0.3

VDD+0.3

V

 

 

 

 

 

 

3

Continuous Current at Digital Outputs

IO

 

40

mA

 

 

 

 

 

 

4

Storage Temperature

TS

-65

+150

°C

 

 

 

 

 

 

5

Package Power Dissipation

PD

 

2

W

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.

 

 

 

Characteristics

 

Sym

 

Min

Typ

Max

 

Units

Test Conditions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

Operating Temperature

 

TOP

-40

 

 

 

+85

 

°C

 

 

 

 

2

 

Positive Supply

 

VDD

4.75

 

5.0

 

5.25

 

V

 

 

 

 

3

 

Input Voltage

 

VI

0

 

 

 

VDD

 

V

 

 

 

 

DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Characteristics

 

Sym

 

Min

 

Typ‡

 

Max

 

Units

 

Test Conditions/Pins

1

 

 

Supply Current at

 

IDD

 

 

 

100

 

160

 

 

mA

Outputs unloaded

 

 

 

19.44 Mbyte/sec & 4 Mbps

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

I

Input High Voltage

 

VIH

 

2.0

 

 

 

 

 

 

V

TTL inputs (most pins)

 

 

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

Input Low Voltage

 

VIL

 

 

 

 

 

0.8

 

 

V

TTL inputs (most pins)

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

U

Input High-Going Threshold

 

VT+

 

 

 

2.8

 

4.2

 

 

V

Schmitt inputs

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

Input Low-Going Threshold

 

VT-

 

0.9

 

1.8

 

 

 

 

V

Schmitt inputs

 

S

 

 

 

 

 

 

 

6

 

Input Leakage (I/O pins)

 

IIL

 

 

 

 

 

50

 

 

μA

VI between VSS and VDD

 

 

 

 

 

 

 

 

 

 

7

 

 

Input Pin Capacitance

 

CI

 

 

 

 

 

10

 

 

pF

 

 

 

 

8

 

 

Output High Voltage

 

VOH

 

2.4

 

 

 

 

 

 

V

Sourcing IOH

9

 

O

Output Low Voltage

 

VOL

 

 

 

 

 

0.4

 

 

V

Sinking IOL

10

 

Output High Current

 

IOH

 

9

 

 

 

 

 

 

mA

Pins: STi4-7, STo4-7

 

U

 

 

 

 

 

 

 

 

 

 

(sourcing at VOH)

 

or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

16

 

 

 

 

 

 

mA

TDO, RPA, DTA, AD7-0, F0,

 

 

or

 

IOL

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

SPCKo, STi0-3, STo0-3

 

 

Output Low Current

 

 

 

 

 

 

 

 

 

 

 

 

 

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(sinking at VOL)

 

 

 

28

 

 

 

 

 

 

mA

PDo0-7, CTo3-0, PPFTo

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

μA

 

 

 

 

11

 

S

High Impedance Leakage

 

IOZ

 

 

 

 

 

5

 

 

VO between VSS and VDD.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pins: PDo0-7, CTo3-0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

Output Pin Capacitance

 

CO

 

 

 

 

 

10

 

 

pF

 

 

 

 

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

2-262

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Page 31 Page 33
Contents
Features ApplicationsPIN Plcc Pin ConnectionsPin Description Pin #Description 100 No ConnectionTDI PckrPckt +5 Volt Power Supply GroundDevice Operation Time Slot Interchange Operation SwitchingFunctional Description C4/8R1&2 4 MHz Serial I/O 2 Mbps Serial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 MbpsPPFRi PDi0-7 Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Receive Path Bypass/Parallel-Switching PathTransmit Path Serial Data Port Parallel Data Port Parallel Port Clock Signals and FramingSerial Frame Pulse Timing and Switching Control Output Driver Enable Control CapabilityTiming Mode 1 TM1 Ring Master Asynchronous Parallel Port With ST-BUS Clock MasterAsynchronous Parallel Port With ST-BUS Clock Slave Timing Mode 2 TM2 Ring SlaveTM1 Multiple-MT90840 Sub-Mode Pfdi TM2 Multiple-MT90840 Sub-Mode Sfdi External PLL and C4 Phase-CorrectionInternal 4.096 MHz Clock Divider Sfdi = MT90840 Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 Throughput Delay MT90840 Per-channel FunctionsPer-channel Bypass on the Parallel Port Per-channel Control Outputs on the Parallel PortMode Data Rates Minimum Delay Total Throughput Delay MT90840 Throughput Delay SummaryPer-channel Message Mode Serial and Parallel STi0 STo0Per-channel Tri-state Serial and Parallel Per-channel Direction Control on the Serial PortSerial Data Memory Addressing Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing Microprocessor Port Address Mapping of the Internal RegistersIRQ Interrupt Pin DTA Data Transfer Acknowledgment PinMT90840 Register Address Mapping Accessing Internal MemoriesHex Clock Quality and TM1 Tpcm Access Integrity Clock Quality and TM2 Rpcm Access IntegrityDetecting Clock Presence Memory Block-ProgrammingTiming Mode Initialization Jtag SupportTest Access Port TAP Boundary-Scan Instruction RegisterI01 Instruction Description Boundary-Scan Instruction RegisterTest Data Registers Cells DefinitionBoundary-Scan Register Cells Definitions HighInterface Mode Selection Register IMS READ/WRITE Timing Mode Register TIM READ/WRITERegister Description DR1General Purpose Mode Register GPM READ/WRITE Alarm Status Register ALS READ/WRITE Phase Status Registers PSD Read Only Control Register CR READ/WRITEInternal Memory Description AB9 AB8AB11 AB10 Distributed Isochronous Network CTI Distributed Architecture Implemented with the MT90840Parameter Symbol Min Max Units Characteristics Sym Min Typ Max Units Test ConditionsCharacteristics Sym Min Typ‡ Max Units Test Conditions/Pins Absolute Maximum RatingsCharacteristics Sym Min Typ‡ Max Units Test Conditions TM1Output Pin Test Point Characteristics Sym Min Typ‡Units Test Conditions Serial Port with Negative Polarity F0 ST-BUS Serial Port with Positive Polarity F0 GCISerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Negative Polarity Spfp = F0 Frame Sync with Positive Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Positive Polarity Spfp = Frame Sync with Negative Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 AC Electrical Characteristics Parallel Data Port Parallel Port Receive TimingParallel Port in Timing Mode RD/WR 774 Up to 3 C4 cycles + Register takd-wrIntel/National Multiplexed Bus Timing AD0AC Electrical Characteristics† Motorola Multiplexed Bus Mode Characteristics Sym MinAD0-7 AD0-13Parameter Symbol Min Max Units Test Conditions Boundary Scan Test Port TimingNot to scale Dimensions in inches are not exactDim Min Max 280
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