Mitel MT90840 manual Control Register CR READ/WRITE, Phase Status Registers PSD Read Only

This register selects which 128 byte page of which internal memory will be accessed by the CPU when the address bit AD<7> is high. (When address bit AD<7> is low, the control registers are accessed.)

SEL2-0Memory Select bits. Used by the CPU to select the internal memories of the MT90840 for read or write operations. SEL2-0 bits have to be written before any READ/WRITE operation is performed on the internal memories.

HA11-7High Address Bits 11-7. These bits select which 128 byte page of the selected memory (see SEL2-0 bits) will be accessed by the CPU. Used along with AD0-AD6 input lines to address the MT90840 internal memories when the address bit AD<7> is high. See RPCM, TPCM, RPDM and TPDM Address Mapping section for more details.

To address serial time slots in TPDM or RPCM:

To address parallel time slots in RPDM or TPCM:

Phase Status Registers (PSD) - READ Only

PSD10-0Phase Status Data 10-0. The PSD bits represent the phase status of the serial port, as sampled at every second PPFRi frame (every 250 μsec). PSD0 is the phase of the internal 4.096 MHz clock, PSD1-9 count the cycles of the 4.096 MHz within a frame, and PSD10 toggles each frame (even/odd frame bit). The PSD bits enable the CPU to monitor the relative phases of the Receive parallel port and the serial port. This is especially useful in TM1, where the PSD bits might be used by the CPU to monitor a PLL control loop, since the elastic buffer in the Receive parallel port allows great variation in phase. These registers should be read twice in succession, in case the CPU access occurs close to the sampling edge.

2-258