Mitel MT90840 manual AB11 AB10

Page 30

MT90840

Preliminary Information

Receive Path Connection Memory High (RPCM High) - This is a 7-bit x 512-position memory. Used only in TM1, 2, & 3.

-

MC

DC

OE

AB11 AB10

AB9

AB8

(RX Path CM High)

7

6

5

4

3

2

1

0

MC Message Channel: The message channel contents are provided by the CPU in bits AB0-7 in the Rx Path Connection Memory Low. If MC is HIGH, the contents of the corresponding location of RPCM Low are output on this serial port channel. If MC is LOW, the contents of the corresponding location in RPCM Low act as an address for the Rx Path Data Memory and so determine the source of the connection (input channels from the PDi0-7 port).

DC Direction Control: DC set HIGH indicates this channel is an output. DC set LOW indicates this channel is an input. The operation of this bit is modified by the state of FDC in the IMS Register.

When FDC = LOW (2.048, 4.096 or 8.192 Mbps) the 512 DC bits (256 at 2.048) each define the direction of a pair of pins for each channel. When DC is set LOW the associated channel on the STo pin becomes an input, and the corresponding channel on the same-number STi pin is automatically used as the output for this time slot. When DC is set HIGH, STo is the output, and STi is the input for this time slot (default).

When FDC = HIGH (2.048 Mbps), the 512 DC bits can be used to control the direction of each individual 64 kbps time slot present on the 16 serial I/O lines on a non-symmetrical basis; i.e. all 512 channels can be configured as outputs or inputs or any mixed combination. If DC is LOW, this serial port channel is defined as input. If DC is HIGH, this channel is defined as output. Note that the CPU still has to set OE to enable the output buffers on each channel defined as an output.

OE Output Enable. Per-channel tristate control for each channel on the serial port side. If FDC is HIGH, the 512 OE bits enable the output for each of the 512 ST channels, unless the channel is defined as an input by the DC bit. In 4.096 and 8.192 Mbps modes, the OE bit enables the output buffer either on a STo pin, or an STi pin, as defined by the accompanying DC bit.

AB8-11Source Channel Address. These 4 bits are used along with AB0-7 to select any of the 2430 parallel incoming channels from the parallel port and determine the switch connection to the 512 possible destination channels on the serial port.

Receive Path Connection Memory Low (RPCM Low) - This is an 8-bit x 512-position memory. Used only in TM1, 2 &3.

AB7

AB6

AB5

AB4

AB3

AB2

AB1

AB0

(RX Path CM Low)

7

6

5

4

3

2

1

0

AB0-7Source Channel Address. In switching mode (MC=LOW), these 8 bits are used along with AB8-11 to select one of the 2430 incoming channels from the parallel port. In message mode (MC=HIGH), these 8 bits are programmed by the CPU with the message patterns desired on the corresponding serial output channel.

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Contents Features ApplicationsPIN Plcc Pin ConnectionsDescription 100 Pin DescriptionPin # No ConnectionPckr PcktTDI +5 Volt Power Supply GroundTime Slot Interchange Operation Switching Functional DescriptionDevice Operation PPFRi PDi0-7 C4/8R1&2 4 MHz Serial I/O 2 MbpsSerial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Bypass/Parallel-Switching Path Transmit PathReceive Path Serial Data Port Parallel Port Clock Signals and Framing Serial Frame PulseParallel Data Port Timing Mode 1 TM1 Ring Master Timing and Switching ControlOutput Driver Enable Control Capability Asynchronous Parallel Port With ST-BUS Clock MasterTiming Mode 2 TM2 Ring Slave TM1 Multiple-MT90840 Sub-Mode PfdiAsynchronous Parallel Port With ST-BUS Clock Slave External PLL and C4 Phase-Correction Internal 4.096 MHz Clock DividerTM2 Multiple-MT90840 Sub-Mode Sfdi Synchronous Parallel Port With ST-BUS Clock Slave Sfdi =Sfdi = MT90840 Per-channel Bypass on the Parallel Port MT90840 Throughput DelayMT90840 Per-channel Functions Per-channel Control Outputs on the Parallel PortMode Data Rates Minimum Delay Total Throughput Delay MT90840 Throughput Delay SummaryPer-channel Tri-state Serial and Parallel Per-channel Message Mode Serial and ParallelSTi0 STo0 Per-channel Direction Control on the Serial PortSerial Data Memory Addressing Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing IRQ Interrupt Pin Microprocessor PortAddress Mapping of the Internal Registers DTA Data Transfer Acknowledgment PinAccessing Internal Memories HexMT90840 Register Address Mapping Detecting Clock Presence Clock Quality and TM1 Tpcm Access IntegrityClock Quality and TM2 Rpcm Access Integrity Memory Block-ProgrammingTiming Mode Initialization Jtag SupportI01 Instruction Description Test Access Port TAPBoundary-Scan Instruction Register Boundary-Scan Instruction RegisterBoundary-Scan Register Cells Definitions Test Data RegistersCells Definition HighRegister Description Interface Mode Selection Register IMS READ/WRITETiming Mode Register TIM READ/WRITE DR1General Purpose Mode Register GPM READ/WRITE Alarm Status Register ALS READ/WRITEPhase Status Registers PSD Read Only Control Register CR READ/WRITEInternal Memory Description AB9 AB8AB11 AB10 Distributed Isochronous Network CTI Distributed Architecture Implemented with the MT90840Characteristics Sym Min Typ‡ Max Units Test Conditions/Pins Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ Max Units Test Conditions Absolute Maximum RatingsCharacteristics Sym Min Typ‡ Max Units Test Conditions TM1Characteristics Sym Min Typ‡ Units Test ConditionsOutput Pin Test Point Serial Port with Negative Polarity F0 ST-BUS Serial Port with Positive Polarity F0 GCISerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Negative Polarity Spfp = F0 Frame Sync with Positive Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Positive Polarity Spfp = Frame Sync with Negative Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 AC Electrical Characteristics Parallel Data Port Parallel Port Receive TimingParallel Port in Timing Mode RD/WR 774 Up to 3 C4 cycles + Register takd-wrIntel/National Multiplexed Bus Timing AD0AC Electrical Characteristics† Motorola Multiplexed Bus Mode Characteristics Sym MinAD0-7 AD0-13Parameter Symbol Min Max Units Test Conditions Boundary Scan Test Port TimingDimensions in inches are not exact Dim Min MaxNot to scale 280

MT90840 specifications

The Mitel MT90840 is an advanced telecommunications device designed to enhance connectivity and communication capabilities for various applications. With its robust array of features and technologies, the MT90840 is well-suited for businesses looking to improve their communications infrastructure.

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In conclusion, the Mitel MT90840 stands out as a versatile and reliable telecommunications solution. Its rich feature set, including voice and data integration, scalability, VoIP capabilities, user-friendly interface, and interoperability, makes it an ideal choice for businesses looking to elevate their communications strategy.
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