Mitel MT90840 Frame Sync with Positive Polarity Spfp =, Frame Sync with Negative Polarity Spfp =

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MT90840			Preliminary Information
	tclk
tt	tclkh	tclkl
C4/8R1**
(8.192 MHz
reference)	tsod
	tsod
STo0-7	bit 0, ch.127	bit 7, ch. 0	bit 6, ch. 0
	bit 0, ch.127	bit 7, ch. 0	bit 6, ch. 0
	tstis	tstih
STi0-7		bit 7
STi0-7
	tdf	tdf
F0o output
(8 kHz)

C4/8R1** (8.192 MHz

reference)

STo0-7

STi0-7

F0o output (8 kHz)

Frame Sync with Positive Polarity (SPFP = 1)

tclk

tt			tclkh		tclkl

tsod
bit 0, ch.127	bit 7, ch. 0	bit 6, ch. 0
tstis	tstih
	bit 7
tdf	tdf
	tdf

Frame Sync with Negative Polarity (SPFP = 0)

**In TM2 and TM3 operation at 8.192 Mbps, the F0 output signal is clocked by the C4/8R1 input reference provided by the user. (In 8.192 Mbps applications, the SPCKo output signal is not used.)

Figure 24 - Serial Port Timing for 8.192 Mbps - Timing Modes 2 and 3

2-270

Image 40

Contents

Features ApplicationsPIN Plcc Pin ConnectionsPin Description Pin #Description 100 No ConnectionPckt PckrTDI +5 Volt Power Supply GroundFunctional Description Time Slot Interchange Operation SwitchingDevice Operation C4/8R1&2 4 MHz Serial I/O 2 Mbps Serial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 MbpsPPFRi PDi0-7 Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Transmit Path Bypass/Parallel-Switching PathReceive Path Serial Data Port Serial Frame Pulse Parallel Port Clock Signals and FramingParallel Data Port Timing and Switching Control Output Driver Enable Control CapabilityTiming Mode 1 TM1 Ring Master Asynchronous Parallel Port With ST-BUS Clock MasterTM1 Multiple-MT90840 Sub-Mode Pfdi Timing Mode 2 TM2 Ring SlaveAsynchronous Parallel Port With ST-BUS Clock Slave Internal 4.096 MHz Clock Divider External PLL and C4 Phase-CorrectionTM2 Multiple-MT90840 Sub-Mode Sfdi Sfdi = Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 MT90840 Throughput Delay MT90840 Per-channel FunctionsPer-channel Bypass on the Parallel Port Per-channel Control Outputs on the Parallel PortMode Data Rates Minimum Delay Total Throughput Delay MT90840 Throughput Delay SummaryPer-channel Message Mode Serial and Parallel STi0 STo0Per-channel Tri-state Serial and Parallel Per-channel Direction Control on the Serial PortSerial Data Memory Addressing Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing Microprocessor Port Address Mapping of the Internal RegistersIRQ Interrupt Pin DTA Data Transfer Acknowledgment PinHex Accessing Internal MemoriesMT90840 Register Address Mapping Clock Quality and TM1 Tpcm Access Integrity Clock Quality and TM2 Rpcm Access IntegrityDetecting Clock Presence Memory Block-ProgrammingTiming Mode Initialization Jtag SupportTest Access Port TAP Boundary-Scan Instruction RegisterI01 Instruction Description Boundary-Scan Instruction RegisterTest Data Registers Cells DeﬁnitionBoundary-Scan Register Cells Deﬁnitions HighInterface Mode Selection Register IMS READ/WRITE Timing Mode Register TIM READ/WRITERegister Description DR1General Purpose Mode Register GPM READ/WRITE Alarm Status Register ALS READ/WRITEPhase Status Registers PSD Read Only Control Register CR READ/WRITEInternal Memory Description AB9 AB8AB11 AB10 Distributed Isochronous Network CTI Distributed Architecture Implemented with the MT90840Parameter Symbol Min Max Units Characteristics Sym Min Typ Max Units Test ConditionsCharacteristics Sym Min Typ‡ Max Units Test Conditions/Pins Absolute Maximum RatingsCharacteristics Sym Min Typ‡ Max Units Test Conditions TM1Units Test Conditions Characteristics Sym Min Typ‡Output Pin Test Point Serial Port with Negative Polarity F0 ST-BUS Serial Port with Positive Polarity F0 GCI Serial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Negative Polarity Spfp = F0 Frame Sync with Positive Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Positive Polarity Spfp = Frame Sync with Negative Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 AC Electrical Characteristics Parallel Data Port Parallel Port Receive TimingParallel Port in Timing Mode RD/WR 774 Up to 3 C4 cycles + Register takd-wrIntel/National Multiplexed Bus Timing AD0AC Electrical Characteristics† Motorola Multiplexed Bus Mode Characteristics Sym MinAD0-7 AD0-13Parameter Symbol Min Max Units Test Conditions Boundary Scan Test Port TimingDim Min Max Dimensions in inches are not exactNot to scale 280