Mitel MT90840 manual Mode Data Rates Minimum Delay Total Throughput Delay

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MT90840

 

Preliminary Information

 

 

 

 

 

 

 

Mode

Data Rates

Minimum Delay

Total Throughput Delay

 

 

 

 

 

 

 

 

TM1, TM2,

All

Dmin = 7.7 μsec

D = Dmin + 1 frame + Po - Si = 132.7 μsec + Po - Si

 

 

or TM3 S/P

 

Note 1

Min. 7.7 μsec, Avg. 133 μsec, Max. 258 μsec

 

 

 

 

 

 

 

 

TM1P/S

All

Dmin = ELDmin

D = 1 frame + ELD + So - Pi = 125 μsec + ELD + So - Pi

 

 

 

 

= 4.4 μsec

Min. 4.4 μsec, Max. 379 μsec

 

 

 

 

Note 2

 

 

 

 

 

 

 

 

 

TM2 P/S

All

Dmin = 4.3 μsec

D = Dmin + 1 frame + So - Pi = 129.3 μsec + So - Pi

 

 

 

 

Note 1

Min. 4.3 μsec, Avg. 129 μsec, Max. 254 μsec

 

 

 

 

 

 

 

 

TM3 P/S

All

Dmin = 1 frame -

T = Dmin + 1 frame + So - Pi = 242.3 μsec + So - Pi

 

 

 

 

7.7 μsec

Min. 117 μsec, Avg. 242 μsec, Max. 367 μsec

 

 

 

 

= 117.3 μsec

 

 

 

 

 

 

 

 

 

TM1 P/P

All

Dmin = 12 μsec +

D = 7.7 μsec + 1 frame + ELD

 

 

(Bypass)

 

1 frame

Min.137 μsec, Max. 262 μsec

 

 

 

 

= 137 μsec

 

 

 

 

 

Note 2

 

 

 

 

 

 

 

 

 

TM2 P/P

19.44 Mbyte/s

 

D = {235 or 235.5} PCKR cycles = 12 μsec

 

 

(Bypass)

16.384 Mbyte/s

Note 3

D = {199 or 199.5} PCKR cycles = 12 μsec

 

 

 

6.480 Mbyte/s

 

D = {80 or 80.5} PCKR cycles = 12 μsec

 

 

 

 

 

 

 

 

TM4 P/P

19.44 & 16.384

Dmin = {3.5 or 4}

D = Dmin + 1 frame + Po - Pi

 

 

(Switching)

Mbyte/s

PCKR cycles

Min. < 0.3 μsec, Avg. 125 μsec, Max. 250 μsec

 

 

 

 

(TCP bit = 1 or 0)

 

 

 

 

 

 

 

 

 

TM1 S/P +

All

Dmin = 12 μsec +

D = 12 μs + 2 frames + Transmission + So - Si

 

 

TM2 P/S

 

1 frame

= 262 μsec + Transmission + So - Si

 

 

 

 

= 137 μsec

 

 

 

 

 

 

 

 

 

TM2 S/P +

All

Dmin = 12 μsec +

D = 12 μsec + 2 frames + Transmission + ELD + So - Si

 

 

TM1 P/S

 

1 frame

= 262 μsec + Transmission + ELD + So - Si

 

 

 

 

= 137.4 μsec

 

 

 

 

 

 

 

 

 

TM1 S/P +

All

Dmin = 4 frames

D = (2 X 12) μsec + 4 frames + 2 X Transmission + ELD

 

 

TM2 P/S +

 

= 500 μsec

+ So - Si = {5 or more integral frames} + So - Si

 

 

TM2 S/P +

 

 

(Note 4)

 

 

TM1 P/S

 

 

 

 

 

 

 

 

 

 

 

TM1 S/P +

All

Dmin = 2 frames

D = (3 X 12) μsec + 2 frames + 2 X Transmission + ELD

 

 

TM2

 

= 250 μsec

+ So - Si

 

 

Bypass +

 

 

= {3 or more integral frames} + So - Si

 

 

TM1 P/S

 

 

(Note 4)

 

 

 

 

 

 

 

 

TM3 S/P +

All

Dmin = 250 μsec

D = (7.7 + 117.3) μsec + 2 frames + So - Si

 

 

TM3 P/S

 

 

= 375 μsec + So - Si

 

 

 

 

 

Min. 250 μsec, Avg. 375 μsec, Max. 500 μsec (Note 4)

 

 

 

 

 

 

 

 

 

Table 1 - MT90840 Throughput Delay Summary

Naming rules:

ELD: ELastic Delay, measured from PPFRi to F0i (4.4 to 129.4 μsec).

P/S:Parallel-to-Serial data path.

Pi:Parallel Input channel time, expressed in delay after PPFRi (0 to 125 μsec).

Po:Parallel Output channel time, expressed in delay after PPFTi/o (0 to 125 μsec).

S/P:Serial-to-Parallel data path.

Si:Serial Input channel time, expressed in delay after F0i/o (0 to 125 μsec). So: Serial Output channel time, expressed in delay after F0i/o (0 to 125 μsec).

Transmission:The delay due to electronic circuits and physical media connecting the parallel ports of two MT90840s. (Assumed to be negligible in TM3.)

Note 1: Exact P/S or S/P delay depends on relative positions of PPFRi and F0 +/- 120 nsec tolerance).

Note 2: Actual TM1 P/S and P/P delay depends on elastic position of PPFRi with respect to F0i (see ELD definition).

Note 3: Bypass delay in TM2: PPFT and PDo ch.0 are co-incident with PDi ch.235 at 19.44 MHz, ch.199 at 16 MHz, and ch.80 at 6.48 MHz. (TCP = 1 delays PDo ch.0 an extra half clock-cycle in TM2).

Note 4: “Round-trip” delay from/to serial ports with the same F0 is always an integral number of frames (plus switching: So - Si).

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Contents Features ApplicationsPIN Plcc Pin ConnectionsPin Description Pin #Description 100 No ConnectionPckt PckrTDI +5 Volt Power Supply GroundFunctional Description Time Slot Interchange Operation SwitchingDevice Operation C4/8R1&2 4 MHz Serial I/O 2 Mbps Serial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 MbpsPPFRi PDi0-7 Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Transmit Path Bypass/Parallel-Switching PathReceive Path Serial Data Port Serial Frame Pulse Parallel Port Clock Signals and FramingParallel Data Port Timing and Switching Control Output Driver Enable Control CapabilityTiming Mode 1 TM1 Ring Master Asynchronous Parallel Port With ST-BUS Clock MasterTM1 Multiple-MT90840 Sub-Mode Pfdi Timing Mode 2 TM2 Ring SlaveAsynchronous Parallel Port With ST-BUS Clock Slave Internal 4.096 MHz Clock Divider External PLL and C4 Phase-CorrectionTM2 Multiple-MT90840 Sub-Mode Sfdi Sfdi = Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 MT90840 Throughput Delay MT90840 Per-channel FunctionsPer-channel Bypass on the Parallel Port Per-channel Control Outputs on the Parallel PortMode Data Rates Minimum Delay Total Throughput Delay MT90840 Throughput Delay SummaryPer-channel Message Mode Serial and Parallel STi0 STo0Per-channel Tri-state Serial and Parallel Per-channel Direction Control on the Serial PortSerial Data Memory Addressing Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing Microprocessor Port Address Mapping of the Internal RegistersIRQ Interrupt Pin DTA Data Transfer Acknowledgment PinHex Accessing Internal MemoriesMT90840 Register Address Mapping Clock Quality and TM1 Tpcm Access Integrity Clock Quality and TM2 Rpcm Access IntegrityDetecting Clock Presence Memory Block-ProgrammingTiming Mode Initialization Jtag SupportTest Access Port TAP Boundary-Scan Instruction RegisterI01 Instruction Description Boundary-Scan Instruction RegisterTest Data Registers Cells DefinitionBoundary-Scan Register Cells Definitions HighInterface Mode Selection Register IMS READ/WRITE Timing Mode Register TIM READ/WRITERegister Description DR1General Purpose Mode Register GPM READ/WRITE Alarm Status Register ALS READ/WRITEPhase Status Registers PSD Read Only Control Register CR READ/WRITEInternal Memory Description AB9 AB8AB11 AB10 Distributed Isochronous Network CTI Distributed Architecture Implemented with the MT90840Parameter Symbol Min Max Units Characteristics Sym Min Typ Max Units Test ConditionsCharacteristics Sym Min Typ‡ Max Units Test Conditions/Pins Absolute Maximum RatingsCharacteristics Sym Min Typ‡ Max Units Test Conditions TM1Units Test Conditions Characteristics Sym Min Typ‡Output Pin Test Point Serial Port with Negative Polarity F0 ST-BUS Serial Port with Positive Polarity F0 GCISerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Negative Polarity Spfp = F0 Frame Sync with Positive Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Positive Polarity Spfp = Frame Sync with Negative Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 AC Electrical Characteristics Parallel Data Port Parallel Port Receive TimingParallel Port in Timing Mode RD/WR 774 Up to 3 C4 cycles + Register takd-wrIntel/National Multiplexed Bus Timing AD0AC Electrical Characteristics† Motorola Multiplexed Bus Mode Characteristics Sym MinAD0-7 AD0-13Parameter Symbol Min Max Units Test Conditions Boundary Scan Test Port TimingDim Min Max Dimensions in inches are not exactNot to scale 280

MT90840 specifications

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