Mitel MT90840 manual Register Description, Interface Mode Selection Register IMS READ/WRITE, DR1

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MT90840

Preliminary Information

Register Description

Interface Mode Selection Register (IMS) - READ/WRITE

DR1

DR0

PPS1 PPS0 ODE

0

0

FDC

7

6

5

4

3

2

1

0

DR1-0Serial Port Data Rate Selection. Select one of three different data rates at the serial inputs and outputs of the MT90840.

DR1

DR0

Data Rate

0

0

2.048 Mbps

01 4.096 Mbps

10 8.192 Mbps

11 reserved

PPS1-0Parallel Port Data Rate Selection. Select one of three different data rates for the parallel port of the MT90840.

PPS1 PPS0

Data Rate

0

0

reserved. Do not use.

0

1

6.480 Mbyte/s.

1

0

19.44 Mbyte/s.

1

1

16.384 Mbyte/s.

ODE Output Drive Enable. When LOW, forces the MT90840 output-buffers on the serial and parallel data ports into the high impedance state (STo0-STo7, STi0-STi7, and PDo0-7). If this output is HIGH, all channels have their output drive enable controlled by the per-channel OE bits of Transmit Connection Memory High, or Receive Connection Memory High.

FDC Full Direction Control. This bit should only be set HIGH at the 2.048 Mbps serial rate. When FDC is set HIGH, each time slot on each of the 16 ST-BUS pins can be individually configured as input or output. Up to 512 serial channels can be “inserted” onto the Transmit parallel port, or up to 512 parallel channels can be “dropped” to the serial port. Individual channel direction is controlled by the DC bits in the RPCM High. When FDC is LOW, the number of input and output time slots are “balanced”, and setting a nominal input to be an output causes the same-number output time slot on the same-number STo pin to become an input. For applications at 4.096 and 8.192 Mbps, this bit should be LOW.

Note: Bits 1 & 2 must be set to 0 by the CPU.

Timing Mode Register (TIM) - READ/WRITE

0

TM1

TM0

C4/8R

TCP

INTCLK SFDI

PFDI

7

6

5

4

3

2

1

0

TM1-0Timing Mode control bits. Define the four different timing modes described in the Timing and Switching Control section.

0 0 Timing Mode 1

0 1 Timing Mode 2

1 0 Timing Mode 3

1 1 Timing Mode 4

C4/8R C4/8R Input Reference Select. If set high, this bit enables the 4.096 or 8.192 MHz serial port reference clock to be taken from input pin C4/8R1. If LOW, the reference is taken from input pin C4/8R2 (default).

TCP Parallel Port Transmit Clock Polarity. To allow the MT90840 parallel port transmit clock to comply with different 155 Mbps framer backplanes, TCP controls which edge of the clock is used to transmit data at the parallel port. (The clock is PCKT in TM1 or PCKR in TM2, 3, & 4). The TCP bit allows the rising (TCP=LOW) or the falling (TCP=HIGH) edges of the transmit clock to be selected.

INTCLK Internal 4.096 MHz Clock Divider. For use in TM2, in 19.44 or 16.384 MHz parallel-port applications. This bit controls the operation of the internal clock divider driven by PCKR. When INTCLK is set HIGH the internal 4.096 MHz clock (and the SPCKo output) are generated by dividing down the PCKR clock. When INTCLK is set LOW, the C4/8R bit controls the source for the serial clock reference. In TM3 and TM4 the MT90840 automatically sets itself in the internal divider mode and the state of INTCLK has no effect. In TM1 this bit is must be set LOW.

SFDI Serial Frame Pulse Direction Control. Normally LOW, unless it is necessary to operate multiple parallel MT90840 devices in Timing Mode 2. When set HIGH, the F0 line becomes an input and this MT90840 is synchronized to the timing of another MT90840 generating the F0o, and using the same 4.096 or 8.192 MHz reference input. One MT90840 in TM2 with SFDI LOW can control several MT80940s with SFDI HIGH. When SFDI is set HIGH, INTCLK is ignored, and SPFP in the GPM register must be set to the expected F0i polarity.

PFDI Parallel Frame Pulse Direction Control. Normally LOW, unless it is necessary to operate multiple parallel MT90840 devices in Timing Mode 1. When set HIGH, the PPFT pin becomes an input and this MT90840 is synchronized to the timing of another MT90840 generating the PPFTo. One MT90840 in TM1 with PFDI LOW can control several MT80940s with PFDI HIGH. When PFDI is HIGH, PPFP in the GPM register must be set to the expected PPFTi polarity.

Note: Bit 7 must be set to 0 by the CPU.

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Contents Features ApplicationsPIN Plcc Pin ConnectionsDescription 100 Pin DescriptionPin # No ConnectionTDI PckrPckt +5 Volt Power Supply GroundDevice Operation Time Slot Interchange Operation SwitchingFunctional Description PPFRi PDi0-7 C4/8R1&2 4 MHz Serial I/O 2 MbpsSerial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Receive Path Bypass/Parallel-Switching PathTransmit Path Serial Data Port Parallel Data Port Parallel Port Clock Signals and FramingSerial Frame Pulse Timing Mode 1 TM1 Ring Master Timing and Switching ControlOutput Driver Enable Control Capability Asynchronous Parallel Port With ST-BUS Clock MasterAsynchronous Parallel Port With ST-BUS Clock Slave Timing Mode 2 TM2 Ring SlaveTM1 Multiple-MT90840 Sub-Mode Pfdi TM2 Multiple-MT90840 Sub-Mode Sfdi External PLL and C4 Phase-CorrectionInternal 4.096 MHz Clock Divider Sfdi = MT90840 Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = Per-channel Bypass on the Parallel Port MT90840 Throughput DelayMT90840 Per-channel Functions Per-channel Control Outputs on the Parallel PortMode Data Rates Minimum Delay Total Throughput Delay MT90840 Throughput Delay SummaryPer-channel Tri-state Serial and Parallel Per-channel Message Mode Serial and ParallelSTi0 STo0 Per-channel Direction Control on the Serial PortSerial Data Memory Addressing Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing IRQ Interrupt Pin Microprocessor PortAddress Mapping of the Internal Registers DTA Data Transfer Acknowledgment PinMT90840 Register Address Mapping Accessing Internal MemoriesHex Detecting Clock Presence Clock Quality and TM1 Tpcm Access IntegrityClock Quality and TM2 Rpcm Access Integrity Memory Block-ProgrammingTiming Mode Initialization Jtag SupportI01 Instruction Description Test Access Port TAPBoundary-Scan Instruction Register Boundary-Scan Instruction RegisterBoundary-Scan Register Cells Definitions Test Data RegistersCells Definition HighRegister Description Interface Mode Selection Register IMS READ/WRITETiming Mode Register TIM READ/WRITE DR1General Purpose Mode Register GPM READ/WRITE Alarm Status Register ALS READ/WRITEPhase Status Registers PSD Read Only Control Register CR READ/WRITEInternal Memory Description AB9 AB8AB11 AB10 Distributed Isochronous Network CTI Distributed Architecture Implemented with the MT90840Characteristics Sym Min Typ‡ Max Units Test Conditions/Pins Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ Max Units Test Conditions Absolute Maximum RatingsCharacteristics Sym Min Typ‡ Max Units Test Conditions TM1Output Pin Test Point Characteristics Sym Min Typ‡Units Test Conditions Serial Port with Negative Polarity F0 ST-BUS Serial Port with Positive Polarity F0 GCISerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Negative Polarity Spfp = F0 Frame Sync with Positive Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Positive Polarity Spfp = Frame Sync with Negative Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 AC Electrical Characteristics Parallel Data Port Parallel Port Receive TimingParallel Port in Timing Mode RD/WR 774 Up to 3 C4 cycles + Register takd-wrIntel/National Multiplexed Bus Timing AD0AC Electrical Characteristics† Motorola Multiplexed Bus Mode Characteristics Sym MinAD0-7 AD0-13Parameter Symbol Min Max Units Test Conditions Boundary Scan Test Port TimingNot to scale Dimensions in inches are not exactDim Min Max 280

MT90840 specifications

The Mitel MT90840 is an advanced telecommunications device designed to enhance connectivity and communication capabilities for various applications. With its robust array of features and technologies, the MT90840 is well-suited for businesses looking to improve their communications infrastructure.

One of the standout features of the Mitel MT90840 is its integration of voice and data services. This allows users to manage their communications more efficiently, streamlining operations and reducing costs. The device supports a wide range of voice codecs, ensuring high-quality audio during calls and providing flexibility for users who may require different standards for different applications.

Another key characteristic of the MT90840 is its scalability. The device is designed to grow with the needs of a business. It supports multiple lines and can be configured to handle an increasing number of users without compromising performance. This scalability is particularly advantageous for organizations that may undergo growth or changes in their communication needs over time.

The Mitel MT90840 also incorporates advanced networking technologies, such as VoIP (Voice over Internet Protocol). This allows users to make voice calls using the internet rather than traditional phone lines, reducing costs for long-distance calls and improving overall communication efficiency. The device is equipped with features that support secure, encrypted communication, further protecting sensitive data and conversations from potential breaches.

Additionally, the MT90840 is designed with user-friendliness in mind. It features an intuitive interface that simplifies operation, making it accessible even for those who may not be tech-savvy. The device is compatible with various peripherals, such as headsets and conferencing equipment, further enhancing its usability in diverse settings, from small offices to large conference rooms.

Moreover, the Mitel MT90840 offers excellent interoperability with a variety of third-party applications. This flexibility enables organizations to integrate the device into their existing systems seamlessly, thereby enhancing productivity without requiring a complete technological overhaul.

In conclusion, the Mitel MT90840 stands out as a versatile and reliable telecommunications solution. Its rich feature set, including voice and data integration, scalability, VoIP capabilities, user-friendly interface, and interoperability, makes it an ideal choice for businesses looking to elevate their communications strategy.
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