Mitel MT90840 manual Internal Memory Description, AB9 AB8

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Preliminary Information

MT90840

Internal Memory Description

Transmit Path Connection Memory High (TPCM High) - This is an 8-bit x 2430-position memory.

OE/

PPBY

MC

CTo1

CTo2/

CTo3/

AB9

AB8

CTo0

AB11

AB10

 

 

 

 

 

7

6

5

4

3

2

1

0

(TX Path CM High)

OE/CTo0 Output Enable. Provides per channel tristate control on the parallel port side. It controls the MT90840 parallel output drivers to disable (tristate, when LOW) or enable (when HIGH) the transmission of data from the device. The contents of this bit will also be clocked out on the CTo0 output pin at the parallel port rate.

PPBY Parallel Port Bypass Enable. Indicates that the parallel output channel is going to contain bypassed (PPBY=HIGH) data from the Receive parallel port of the MT90840. The channels that are not bypassed (PPBY=LOW) can be used for switching of data from the serial port side, or for message-mode data. The use of this bit is only allowed in Timing Modes 1 and 2. The PPBY bit is overridden by MC set HIGH.

MC Message Channel. The message channel contents are programmed by the CPU into the TP Connection Memory Low. If MC=1 the contents of the corresponding location of TPCM Low are output on the corresponding channel at the Transmit parallel port. If MC=LOW, the contents of the programmed location in TPCM Low act as an address for the Data Memory, and so determine the source channel for this output channel. Depending on the timing mode selected, the source of the connection can be an input channel from either serial (TM1, 2, or 3) or parallel (TM4) data ports. This bit overrides PPBY if both are set HIGH.

CTo1-3External Control Lines 1-3. These three bits are used by the CPU to program the three external control pins CTo1-3. Like OE/CTo0, the contents of these lines will be transmitted to pins CTo1-3 at the parallel port rate. Note: CTo2 and CTo3 cannot be used in Timing Mode 4.

AB8-11Source Channel Address Bits 8-11. These bits are used along with bits AB0-7 in TPCM Low to select the source channel for this output channel. In all timing modes except TM4, only bit AB8 is used, along with bits AB0-7 in TPCM Low, to select one of 512 serial source channels from the serial port side to be transmitted on this output channel.

Transmit Path Connection Memory Low (TPCM Low) - This is an 8-bit x 2430-position memory.

AB7

AB6

AB5

AB4

AB3

AB2

AB1

AB0

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

(TX Path CM Low)

AB7-0Source Channel Address Bits. In Timing Modes 1, 2, and 3, these 8 bits are used along with bit AB8 in the TPCM High to select up to 512 serial source channels from the serial port side to be connected to any 512 (out of 2430) output channels available on the parallel port side. See table for details.

In Timing Mode 4, these 8 bits are used along with bits AB8-11 in the TPCM High memory to select up to 2430 source channels from the parallel port input to be connected to any of the 2430 channels available on the parallel port output side.

If message mode is selected at TPCM High bits, the contents of the AB0-7 bits in the TPCM Low locations are transmitted to the corresponding channels at the PDo0-7 lines until the mode is changed by the CPU.

USE OF THE TPCM HIGH AND LOW ADDRESS BITS WHEN SELECTING SOURCE SERIAL-PORT CHANNELS (TM1, TM2 and TM3)

SERIAL STREAM and CHANNEL ALLOCATION

SOURCE STREAM ADDRESSING

SOURCE CHANNEL ADDRESSING

 

 

 

 

 

 

2 Mbps

16 i/o (512 channels)

AB5,AB6,AB7,AB8 (up to 16 streams)

AB0 to AB4 used to select up to 32 channels

 

 

 

 

 

per stream

 

 

 

 

 

 

4 Mbps

8i x 8o (512 channels)

AB6, AB7, AB8 used to select up to 8

AB0 to AB5 used to select up to 64 channels

 

 

 

streams

per stream

 

 

 

 

 

 

8 Mbps

4i x 4o (512 channels)

AB7, AB8 used to select up to 4 streams

AB0 to AB6 used to select up to 128

 

 

 

 

 

channels per stream

 

 

 

 

 

 

 

 

 

 

 

SOURCE CHANNEL ADDRESSING IN TM4

 

 

 

 

 

 

 

 

6.48 Mbyte/s

 

AB0-AB9 (one of 810 input channels)

 

 

 

 

 

 

 

16.384 Mbyte/s

 

AB0 - AB10 (one of 2048 input channels)

 

 

 

 

 

 

 

19.44 Mbyte/s

 

AB0 - AB11 (one of 2430 input channels)

 

 

 

 

 

 

 

 

2-259

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Contents Applications FeaturesPin Connections PIN PlccPin # Pin DescriptionDescription 100 No ConnectionTDI PckrPckt Ground +5 Volt Power SupplyDevice Operation Time Slot Interchange Operation SwitchingFunctional Description Serial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps C4/8R1&2 4 MHz Serial I/O 2 MbpsPPFRi PDi0-7 Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Receive Path Bypass/Parallel-Switching PathTransmit Path Serial Data Port Parallel Data Port Parallel Port Clock Signals and FramingSerial Frame Pulse Output Driver Enable Control Capability Timing and Switching ControlTiming Mode 1 TM1 Ring Master Asynchronous Parallel Port With ST-BUS Clock MasterAsynchronous Parallel Port With ST-BUS Clock Slave Timing Mode 2 TM2 Ring SlaveTM1 Multiple-MT90840 Sub-Mode Pfdi TM2 Multiple-MT90840 Sub-Mode Sfdi External PLL and C4 Phase-CorrectionInternal 4.096 MHz Clock Divider Sfdi = MT90840 Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 Per-channel Functions MT90840 Throughput DelayPer-channel Bypass on the Parallel Port Per-channel Control Outputs on the Parallel PortMT90840 Throughput Delay Summary Mode Data Rates Minimum Delay Total Throughput DelaySTi0 STo0 Per-channel Message Mode Serial and ParallelPer-channel Tri-state Serial and Parallel Per-channel Direction Control on the Serial PortAddressing Serial Data Memory Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing Address Mapping of the Internal Registers Microprocessor PortIRQ Interrupt Pin DTA Data Transfer Acknowledgment PinMT90840 Register Address Mapping Accessing Internal MemoriesHex Clock Quality and TM2 Rpcm Access Integrity Clock Quality and TM1 Tpcm Access IntegrityDetecting Clock Presence Memory Block-ProgrammingJtag Support Timing Mode InitializationBoundary-Scan Instruction Register Test Access Port TAPI01 Instruction Description Boundary-Scan Instruction RegisterCells Definition Test Data RegistersBoundary-Scan Register Cells Definitions HighTiming Mode Register TIM READ/WRITE Interface Mode Selection Register IMS READ/WRITERegister Description DR1Alarm Status Register ALS READ/WRITE General Purpose Mode Register GPM READ/WRITEControl Register CR READ/WRITE Phase Status Registers PSD Read OnlyAB9 AB8 Internal Memory DescriptionAB11 AB10 CTI Distributed Architecture Implemented with the MT90840 Distributed Isochronous NetworkCharacteristics Sym Min Typ Max Units Test Conditions Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ‡ Max Units Test Conditions/Pins Absolute Maximum RatingsTM1 Characteristics Sym Min Typ‡ Max Units Test ConditionsOutput Pin Test Point Characteristics Sym Min Typ‡Units Test Conditions Serial Port with Positive Polarity F0 GCI Serial Port with Negative Polarity F0 ST-BUSSerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Positive Polarity Spfp = F0 Frame Sync with Negative Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Negative Polarity Spfp = Frame Sync with Positive Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 Parallel Port Receive Timing AC Electrical Characteristics Parallel Data PortParallel Port in Timing Mode 774 Up to 3 C4 cycles + Register takd-wr RD/WRAD0 Intel/National Multiplexed Bus TimingCharacteristics Sym Min AC Electrical Characteristics† Motorola Multiplexed Bus ModeAD0-13 AD0-7Boundary Scan Test Port Timing Parameter Symbol Min Max Units Test ConditionsNot to scale Dimensions in inches are not exactDim Min Max 280

MT90840 specifications

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