Mitel MT90840 manual Test Access Port TAP, Boundary-Scan Instruction Register

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MT90840

Preliminary Information

I/O pin of the IC. The operation of the boundary-scan circuitry is controlled by a Test Access Port (TAP) Controller.

Test Access Port (TAP)

The Test Access Port (TAP) has five signals and provides access to the test logic defined by the JTAG standard.

The TAP has the following connections:

•Test Clock Input (TCK)

TCK provides the clock for the test logic. TCK is independent of the MT90840 functional clocks; this permits serial shifting of test data along the Boundary-Scan chain concurrent with the normal operation of the MT90840.

•Test Mode Select Input (TMS)

The signal at TMS selects the operational mode of the TAP Controller. The TMS signals are sampled on the rising edge of TCK. This pin is pulled high internally when not driven.

•The Test Data Input (TDI)

Serial instructions and test-data are shifted in at this pin. Serial information is passed to the instruction register, the boundary scan (test) register, or the bypass register, depending on the present mode of the TAP controller. TDI is sampled on the rising edge of TCK. This pin is pulled high internally when not driven.

•The Test Data Output (TDO)

Serial data is shifted out on this pin. Depending on the present mode of the TAP controller, data will come from one of: the instruction register, the boundary scan register or the bypass register. TDO is clocked out on the falling edge of TCK. When no data is being shifted, the TDO driver is set to a high-impedance state.

•TRST:(Test reset input)

Asynchronously initializes the TAP controller by putting it in the Test-Logic-Resetstate. This pin is pulled high internally when not driven.

One additional pin influences the boundary scan test operation:

•IC: (Manufacturing test pin)

This pin is an IEEE 1149 compliance-enable pin, and must be connected to Vss for proper boundary scan operation (and normal chip operation).

Boundary-Scan Instruction Register

In accordance with the IEEE 1149.1 standard, the MT90840 uses public instructions listed in Table 3 - “Instruction Register”. The MT90840 JTAG Interface contains a two bit instruction register. Instructions are serially loaded into the Instruction Register from the TDI pin when the TAP Controller is in its Shift-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDI and TDO during data register scanning.

I[0:1]

Instruction

 

Description

 

 

 

 

[00]

EXTEST

Boundary-Scan

This instruction is specifically provided to allow board-level interconnect

 

 

Register selected,

testing of opens, bridging errors etc.

 

 

Test enabled

When the EXTEST instruction is executed, the MT90840 core logic is

 

 

 

isolated from the I/O pins, and the state of the I/O pins is determined by

 

 

 

the boundary-scan register. I/O data for this instruction is pre-loaded into

 

 

 

the boundary-scan register with the SAMPLE/PRELOAD instruction.

 

 

 

 

[01]

SAMPLE/

Boundary-Scan

Two functions can be performed by the use of this instruction. It allows a

[10]

PRELOAD

Register selected,

SAMPLE (‘snapshot’) of the normal operation of the MT90840 to be

 

 

Test disabled

taken for examination. And, prior to the selection of another test

 

 

 

operation, a PRELOAD can place data values into the latched parallel

 

 

 

outputs of the Boundary-Scan cells. During the execution of the

 

 

 

instruction, the on-chip logic operation is not hampered in any way.

 

 

 

 

[11]

BYPASS

Bypass Register

This instruction is used to BYPASS the MT90840 while performing

 

 

selected,

boundary-scan testing on other devices with scan registers in the same

 

 

Test disabled

serial register chain. The MT90840 is allowed to function normally. This

 

 

 

instruction is automatically loaded upon

TRST,

as specified in

 

 

 

IEEE1149.1

 

 

 

 

 

 

Table 3 - Boundary-Scan Instruction Register

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Contents Features ApplicationsPIN Plcc Pin ConnectionsPin Description Pin #Description 100 No ConnectionPckr PcktTDI +5 Volt Power Supply GroundTime Slot Interchange Operation Switching Functional DescriptionDevice Operation C4/8R1&2 4 MHz Serial I/O 2 Mbps Serial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 MbpsPPFRi PDi0-7 Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Bypass/Parallel-Switching Path Transmit PathReceive Path Serial Data Port Parallel Port Clock Signals and Framing Serial Frame PulseParallel Data Port Timing and Switching Control Output Driver Enable Control CapabilityTiming Mode 1 TM1 Ring Master Asynchronous Parallel Port With ST-BUS Clock MasterTiming Mode 2 TM2 Ring Slave TM1 Multiple-MT90840 Sub-Mode PfdiAsynchronous Parallel Port With ST-BUS Clock Slave External PLL and C4 Phase-Correction Internal 4.096 MHz Clock DividerTM2 Multiple-MT90840 Sub-Mode Sfdi Synchronous Parallel Port With ST-BUS Clock Slave Sfdi =Sfdi = MT90840 MT90840 Throughput Delay MT90840 Per-channel FunctionsPer-channel Bypass on the Parallel Port Per-channel Control Outputs on the Parallel PortMode Data Rates Minimum Delay Total Throughput Delay MT90840 Throughput Delay SummaryPer-channel Message Mode Serial and Parallel STi0 STo0Per-channel Tri-state Serial and Parallel Per-channel Direction Control on the Serial PortSerial Data Memory Addressing Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing Microprocessor Port Address Mapping of the Internal RegistersIRQ Interrupt Pin DTA Data Transfer Acknowledgment PinAccessing Internal Memories HexMT90840 Register Address Mapping Clock Quality and TM1 Tpcm Access Integrity Clock Quality and TM2 Rpcm Access IntegrityDetecting Clock Presence Memory Block-ProgrammingTiming Mode Initialization Jtag SupportTest Access Port TAP Boundary-Scan Instruction RegisterI01 Instruction Description Boundary-Scan Instruction RegisterTest Data Registers Cells DefinitionBoundary-Scan Register Cells Definitions HighInterface Mode Selection Register IMS READ/WRITE Timing Mode Register TIM READ/WRITERegister Description DR1General Purpose Mode Register GPM READ/WRITE Alarm Status Register ALS READ/WRITEPhase Status Registers PSD Read Only Control Register CR READ/WRITEInternal Memory Description AB9 AB8AB11 AB10 Distributed Isochronous Network CTI Distributed Architecture Implemented with the MT90840Parameter Symbol Min Max Units Characteristics Sym Min Typ Max Units Test ConditionsCharacteristics Sym Min Typ‡ Max Units Test Conditions/Pins Absolute Maximum RatingsCharacteristics Sym Min Typ‡ Max Units Test Conditions TM1Characteristics Sym Min Typ‡ Units Test ConditionsOutput Pin Test Point Serial Port with Negative Polarity F0 ST-BUS Serial Port with Positive Polarity F0 GCISerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Negative Polarity Spfp = F0 Frame Sync with Positive Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Positive Polarity Spfp = Frame Sync with Negative Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 AC Electrical Characteristics Parallel Data Port Parallel Port Receive TimingParallel Port in Timing Mode RD/WR 774 Up to 3 C4 cycles + Register takd-wrIntel/National Multiplexed Bus Timing AD0AC Electrical Characteristics† Motorola Multiplexed Bus Mode Characteristics Sym MinAD0-7 AD0-13Parameter Symbol Min Max Units Test Conditions Boundary Scan Test Port TimingDimensions in inches are not exact Dim Min MaxNot to scale 280

MT90840 specifications

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