HP sv6 manual Introduction, Interface, Procedure

hp scalable visualization digital compositor

compositor self-test sequence

compositor self-test sequence

introduction

All compositor cards are assumed to be fully functional before they are installed in a compositor chassis. They are all individually and functionally tested at the manufacturer. Once they are installed in the compositor backplane, however, they could fail by not being seated properly or by having bent bus pins. This test is a check of backplane connections to ensure that they are functional. This test is simply pass / fail, with the only feedback being which card failed.

interface

This test uses the standard serial communications to the Field Programmable Gate Arrays (FGPA) on the controller card. Both controller FPGAs have registers allowing the controller to read the data values on the video data bus input pins. One of the two FPGAs also has the ability to drive a test value onto its video data bus output.

procedure

This test is performed as part of the compositor initialization on power-up. First, the controller steps through all of the slots on the backplane, identifying the card type. At this point. invalid configurations are identified. Invalid configurations consist of configurations that have an output card with no card before it or an input card that has no card after it.

If the configuration is valid, then all cards are programmed. Card programming is verified by a successful serial transfer to each FPGA after programming. If a card fails the serial transfer test, it is identified as a failure. If one or more FPGA fails the serial transfer test, compositor initialization is aborted, and the failing cards are identified.

The ability of the cards to be configured and then communicate, tests all of the control signals to the cards. The video data bus remains to be tested. The controller tests these signals by instructing each FPGA to drive a specific bit pattern onto the video data bus, using the bus test registers. These test values are then read by the following I/O cards, and

Appendix A 105