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AMD SC2200 Manual

429 pages3.28 Mb

3Contents
5List of Figures
9List of Tables
131.0Overview
- 1.1 General Description
  - Figure 1-1. Block Diagram
  - GX1
  - Video Processor
  - Core Logic SuperI/O
- 141.2 Features
  - General Features
172.0Architecture Overview
- 2.1 GX1 Module
  - 2.1.1 Memory Controller
  - 18Table 2-1. SC2200 Memory Controller Register Summary
  - Table 2-2. SC2200 Memory Controller Registers
  - 21Table 2-2. SC2200 Memory Controller Registers (Continued)
  - 2.1.2 Fast-PCI Bus
  - 2.1.3 Display
- 222.2 Video Processor Module
  - 2.2.1 GX1 Module Interface
  - 2.2.2 Video Input Port
  - 2.2.3 Core Logic Module Interface
  - 2.2.4 CRT DAC
- 232.3 Core Logic Module
  - 2.3.1 Other Interfaces of the Core Logic Module
- 2.4 SuperI/O Module
- 242.5 Clock, Timers, and Reset Logic
  - 2.5.1 Reset Logic
    - AMD Geode SC2200 Processor Data Book 25
    - Signal Definitions 32580B
    - appropriate functional group.
253.0Signal Definitions
- TFT Interface
- Parallel Port/
- CRT
- System
- Figure 3-1. Signal Groups
- ACCESS.bus
- IDE/TFT
- Memory
- Video Port
  - AMD Geode SC2200 Processor
    - Straps
  - Note:
- 26Figure 3-1. Signal Groups (Continued)
- Serial Ports
- GPIO/LPC Bus
- JTAG
- Power
- AC97 Audio
- Test an d
- IR Port
- USB
- Sub-ISA/PCI Bus
- (UARTs)/IDE
- Management
- Measurement
  - AMD Geode SC2200 Processor
- 273.1 Ball Assignments
  - Table 3-1. Signal Definitions Legend
- (Top View)
  - Figure 3-2. BGU481 Ball Assignment Diagram
    - Note: Signal names have been abbreviated in this figure due to space constraints.
    - = GND Ball = PWR Ball = Strap Option Ball = Multiplexed Ball
28AMD Geode SC2200 Processor
- 29Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number
  - 3232 AMD Geode SC2200 Processor Data Book
  - 32580B
- 39Table 3-3. BGU481 Ball Assignment - Sorted Alphabetically by Signal Name
- 433.2 Strap Options
  - Table 3-4. Strap Options
- 443.3 Multiplexing Configuration
  - Table 3-5. Two-Signal/Group Multiplexing
  - 45Table 3-5. Two-Signal/Group Multiplexing (Continued)
  - 46Table 3-6. Three-Signal/Group Multiplexing
  - 47Table 3-6. Three-Signal/Group Multiplexing (Continued)
  - Table 3-7. Four-Signal/Group Multiplexing
- 483.4 Signal Descriptions
  - 3.4.1 System Interface
  - 493.4.1 System Interface (Continued)
  - 503.4.2 Memory Interface Signals
  - 513.4.2 Memory Interface Signals (Continued)
  - 3.4.3 Video Port Interface Signals
  - 523.4.4 CRT/TFT Interface Signals
  - 3.4.5 ACCESS.bus Interface Signals
  - 533.4.5 ACCESS.bus Interface Signals (Continued)
  - 3.4.6 PCI Bus Interface Signals
  - 573.4.7 Sub-ISA Interface Signals
  - 583.4.8 Low Pin Count (LPC) Bus Interface Signals
  - 593.4.9 IDE Interface Signals
  - 603.4.10 Universal Serial Bus (USB) Interface Signals
  - 3.4.11 Serial Ports (UARTs) Interface Signals
  - 613.4.11 Serial Ports (UARTs) Interface Signals (Continued)
  - 623.4.12 Parallel Port Interface Signals
  - 633.4.12 Parallel Port Interface Signals (Continued)
  - 3.4.13 Fast Infrared (IR) Port Interface Signals
  - 643.4.14 AC97 Audio Interface Signals
  - 3.4.15 Power Management Interface Signals
  - 653.4.15 Power Management Interface Signals (Continued)
  - 663.4.16 GPIO Interface Signals
  - 673.4.17 Debug Monitoring Interface Signals
  - 3.4.18 JTAG Interface Signals
  - 683.4.18 JTAG Interface Signals (Continued)
  - 3.4.19 Test and Measurement Interface Signals
  - 3.4.20 Power, Ground and No Connections1
  - 693.4.20 Power, Ground and No Connections1 (Continued)
714.0General Configuration Block
- 4.1 Configuration Block Addresses
  - Table 4-1. General Configuration Block Register Summary
- 724.2 Multiplexing, Interrupt Selection, and Base Address Registers
  - Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers
- 794.3 WATCHDOG
  - 4.3.1 Functional Description
  - Figure 4-1. WATCHDOG Block Diagram
  - WATCHDOG
  - 804.3.2 WATCHDOG Registers
  - Table 4-3. WATCHDOG Registers
- 814.4 High-Resolution Timer
  - 4.4.1 Functional Description
  - 4.4.2 High-Resolution Timer Registers
  - Table 4-3. WATCHDOG Registers (Continued)
  - 82Table 4-4. High-Resolution Timer Registers
- 834.5 Clock Generators and PLLs
  - Note: VPLL2 powers PLL2 and PLL5. VPLL3 powers PLL3, PLL4, and PLL6.
  - Figure 4-2. Clock Generation Block Diagram
  - 844.5.1 27 MHz Crystal Oscillator
  - Figure 4-3. Recommended Oscillator External Circuitry
  - Table 4-5. Crystal Oscillator Circuit Components
  - 854.5.2 GX1 Module Core Clock
  - 4.5.3 Internal Fast-PCI Clock
  - Table 4-6. Core Clock Frequency
  - Table 4-7. Strapped Core Clock Frequency
  - 864.5.4 SuperI/O Clocks
  - 4.5.5 Core Logic Module Clocks
  - 4.5.6 Video Processor Clocks
  - 874.5.7 Clock Registers
    - Table 4-9 describes the registers of the clock generator and PLL.
  - Table 4-8. Clock Generator Configuration
  - 88Table 4-8. Clock Generator Configuration (Continued)
895.0SuperI/O Module
- Figure 5-1. SIO Block Diagram
- 905.1 Features
- 915.2 Module Architecture
  - Figure 5-2. Detailed SIO Block Diagram
- 925.3 Configuration Structure/Access
  - 5.3.1 Index-Data Register Pair
  - 5.3.2 Banked Logical Device Registers
  - Figure 5-3. Structure of the Standard Configuration Register File
  - Table 5-1. SIO Configuration Options
  - Table 5-2. LDN Assignments
  - 935.3.3 Default Configuration Setup
  - 5.3.4 Address Decoding
- 945.4 Standard Configuration Registers
  - Figure 5-4. Standard Configuration Registers Map
  - 96Table 5-3. Standard Configuration Registers
  - 975.4.1 SIO Control and Configuration Registers
  - Table 5-4. SIO Control and Configuration Register Map
  - Table 5-5. SIO Control and Configuration Registers
  - 985.4.2 Logical Device Control and Configuration
  - Table 5-6. Relevant RTC Configuration Registers
  - 99Table 5-7. RTC Configuration Registers
  - 100Table 5-8. Relevant SWC Registers
  - 101Table 5-9. Relevant IRCP/SP3 Registers
  - Table 5-10. IRCP/SP3 Configuration Register
  - 102Table 5-11. Relevant Serial Ports 1 and 2 Registers
  - Table 5-12. Serial Ports 1 and 2 Configuration Registe r
  - 103Table 5-13. Relevant ACB1 and ACB2 Registers
  - Table 5-14. ACB1 and ACB2 Configuration Register
  - 104Table 5-15. Relevant Parallel Port Registers
  - Table 5-16. Parallel Port Configuration Register
- 1055.5 Real-Time Clock (RTC)
  - 5.5.1 Bus Interface
  - 5.5.2 RTC Clock Generation
  - Figure 5-5. Recommended Oscillator External Circuitry
  - Table 5-17. Crystal Oscillator Circuit Components
  - 106Figure 5-6. External Oscillator Connections
  - Figure 5-7. Divider Chain Control
  - 108Figure 5-8. Power Supply Connections
  - Figure 5-9. Typical Battery Configuration
  - Figure 5-10. Typical Battery Current: Battery Backed Power Mode @ TC = 25C
  - Figure 5-11. Typical Battery Current: Normal Operation Mode
  - 109Table 5-18. System Power States
  - 110Figure 5-12. Interrupt/Status Timing
  - 1115.5.3 RTC Registers
  - Table 5-19. RTC Register Map
  - Table 5-20. RTC Registers
  - 113Table 5-20. RTC Registers (Continued)
  - 114Table 5-21. Divider Chain Control / Test Selection
  - Table 5-22. Periodic Interrupt Rate Encoding
  - Table 5-23. BCD and Binary Formats
  - 1155.5.4 RTC General-Purpose RAM Map Table 5-24. Standard RAM Map
  - Table 5-25. Extended RAM Map
- 1165.6 System Wakeup Control (SWC)
  - 5.6.1 Event Detection
  - Table 5-26. Time Range Limits for CEIR Protocols
  - 1175.6.2 SWC Registers
  - Table 5-27. Banks 0 and 1 - Common Control and Status Register Map
  - Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map
  - 118Table 5-29. Banks 0 and 1 - Common Control and Status Registers
  - 119Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers
  - 120Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers (Continued)
- 1215.7 ACCESS.bus Interface
  - 5.7.1 Data Transactions
  - Figure 5-14. Start and Stop Conditions
  - Figure 5-13. Bit Transfer 5.7.2 Start and Stop Conditions
  - 1225.7.3 Acknowledge (ACK) Cycle
  - Figure 5-15. ACCESS.bus Data Transaction
  - Figure 5-16. ACCESS.bus Acknowledge Cycle
  - 1235.7.4 Acknowledge After Every Byte Rule
  - 5.7.5 Addressing Transfer Formats
  - 5.7.6 Arbitration on the Bus
  - 5.7.7 Master Mode
  - Figure 5-17. A Complete ACCESS.bus Data Transaction
  - 1255.7.8 Slave Mode
  - or
  - 5.7.9 Configuration
  - 1265.7.10 ACB Registers
  - Table 5-31. ACB Register Map
  - Table 5-32. ACB Registers
  - 128Table 5-32. ACB Registers (Continued)
- 1295.8 Legacy Functional Blocks
  - 5.8.1 Parallel Port
  - Table 5-33. Parallel Port Register Map for First Level Offset
  - Table 5-34. Parallel Port Register Map for Second Level Offset
  - 130Table 5-35. Parallel Port Bit Map for First Level Offset
  - Table 5-36. Parallel Port Bit Map for Second Level Offset
  - 1315.8.2 UART Functionality (SP1 and SP2)
  - Figure 5-18. UART Mode Register Bank Architecture
  - Table 5-37. Bank 0 Register Map
  - 132Table 5-38. Bank Selection Encoding
  - Table 5-39. Bank 1 Register Map
  - Table 5-40. Bank 2 Register Map
  - 133Table 5-41. Bank 3 Register Map
  - Table 5-42. Bank 0 Bit Map
  - 134Table 5-43. Bank 1 Bit Map
  - Table 5-44. Bank 2 Bit Map
  - Table 5-45. Bank 3 Bit Map
  - 1355.8.3 IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality
  - Figure 5-19. IRCP/SP3 Register Bank Architecture
  - Table 5-46. Bank 0 Register Map
  - 136Table 5-47. Bank Selection Encoding
  - Table 5-48. Bank 1 Register Map
  - Table 5-49. Bank 2 Register Map
  - 137Table 5-50. Bank 3 Register Map
  - Table 5-51. Bank 4 Register Map
  - Table 5-52. Bank 5 Register Map
  - 138Table 5-53. Bank 6 Register Map
  - Table 5-54. Bank 7 Register Map
  - Table 5-55. Bank 0 Bit Map
  - 139Table 5-56. Bank 1 Bit Map
  - Table 5-57. Bank 2 Bit Map
  - Table 5-58. Bank 3 Bit Map
  - Table 5-59. Bank 4 Bit Map
  - 140Table 5-59. Bank 4 Bit Map (Continued)
  - Table 5-60. Bank 5 Bit Map
  - Table 5-61. Bank 6 Bit Map
  - Table 5-62. Bank 7 Bit Map
1416.0Core Logic Module
- 6.1 Feature List
- 1426.2 Module Architecture
  - Figure 6-1. Core Logic Module Block Diagram
  - 1436.2.1 Fast-PCI Interface to External PCI Bus
  - 6.2.2 PSERIAL Interface
  - 1446.2.3 IDE Controller
  - 145Table 6-1. Physical Region Descriptor Format
  - 146Table 6-2. UltraDMA/33 Signal Definitions
  - 1476.2.4 Universal Serial Bus
  - 6.2.5 Sub-ISA Bus Interface
  - 148Figure 6-2. Non-Posted Fast-PCI to ISA Access
  - 149Figure 6-3. PCI to ISA Cycles with Delayed Transaction Enabled
  - 150Figure 6-4. ISA DMA Read from PCI Memory
  - Figure 6-5. ISA DMA Write to PCI Memory
  - 151Table 6-3. Cycle Multiplexed PCI / Sub-ISA Balls
  - 152Figure 6-6. PCI Change to Sub-ISA and Back 6.2.6 AT Compatibility Logic
  - 154Figure 6-7. PIT Timer
  - 155Figure 6-8. PIC Interrupt Controllers
  - Table 6-4. PIC Interrupt Mapping
  - 156Figure 6-9. PCI and IRQ Interrupt Mapping 6.2.7 I/O Ports 092h and 061h System Control
  - 1576.2.8 Keyboard Support
  - Figure 6-10. SMI Generation for NMI
  - 1586.2.9 Power Management Logic
  - 159Table 6-5. Wakeup Events Capability
  - 160Table 6-6. Power Planes Control Signals vs. Sleep States
  - Table 6-7. Power Planes vs. Sleep/Global States
  - Table 6-8. Power Management Events
  - 1626.2.10 Power Management Programming
  - 165Figure 6-11. General Purpose Timer and UDEF Trap SMI Tree Example
  - 166Table 6-9. Device Power Management Programming Summary
  - 1676.2.11 GPIO Interface
  - 6.2.12 Integrated Audio
  - Table 6-10. Bus Masters That Drive Specific Slots of the AC97 Interface
  - 168Table 6-11. Physical Region Descriptor Format
  - 169Figure 6-12. PRD Table Example
  - 170Figure 6-13. AC97 V2.0 Codec Signal Connections
  - AMD Geode SC2200 Processor
  - 172Figure 6-14. Audio SMI Tree Example
    - GX1 Core Logic Module
    - Module
  - 173Figure 6-15. Typical Setup
  - 174Table 6-12. Cycle Types
- 1756.3 Register Descriptions
  - 6.3.1 PCI Configuration Space and Access Methods
  - Table 6-13. PCI Configuration Address Register (0CF8h)
  - 1766.3.2 Register Summary
  - Table 6-14. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support Summary
  - 179Table 6-15. F0BAR0: GPIO Support Registers Summary
  - Table 6-16. F0BAR1: LPC Support Registers Summary
  - 180Table 6-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary
  - Table 6-18. F1BAR0: SMI Status Registers Summary
  - 181Table 6-19. F1BAR1: ACPI Support Registers Summary
  - 182Table 6-20. F2: PCI Header Registers for IDE Controller Support Summary
  - 183Table 6-21. F2BAR4: IDE Controller Support Registers Summary
  - Table 6-22. F3: PCI Header Registers for Audio Support Summary
  - 184Table 6-23. F3BAR0: Audio Support Registers Summary
  - 185Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary
  - Table 6-25. F5BAR0: I/O Control Support Registers Summary
  - 186Table 6-26. PCIUSB: USB PCI Configuration Register Summary
  - 187Table 6-27. USB_BAR: USB Controller Registers Summary
  - 188Table 6-28. ISA Legacy I/O Register Summary
  - 189Table 6-28. ISA Legacy I/O Register Summary (Continued)
- 1906.4 Chipset Register Space
  - 6.4.1 Bridge, GPIO, and LPC Registers - Function 0
  - Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Suppo rt
  - 223Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers
  - 227Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers
  - 2356.4.2 SMI Status and ACPI Registers - Function 1
  - Table 6-32. F1: PCI Header Registers for SMI Status and ACPI Support
  - 236Table 6-33. F1BAR0+I/O Offset: SMI Status Registers
    - are located. Table 6-34 shows the I/O mapped ACPI Sup- port registers accessed through F1BAR1.
  - 245Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers
  - 2546.4.3 IDE Controller Registers - Function 2
  - Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration
    - mats of the I/O mapped IDE Controller Configuration registers that are accessed through F2BAR4.
  - 258Table 6-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers
  - 259Table 6-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers (Continued)
  - 2606.4.4 Audio Registers - Function 3
  - Table 6-37. F3: PCI Header Registers for Audio Configuration
    - memory mapped audio configuration registers that are accessed through F3BAR0.
  - 261Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers
  - 2756.4.5 X-Bus Expansion Interface - Function 5
  - Table 6-39. F5: PCI Header Registers for X-Bus Expansion
    - trol support registers. Table 6-40 shows the support regis- ters accessed through F5BAR0.
  - 278Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Registers
  - 279Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Regist ers (Continued)
  - 2806.4.6 USB Controller Registers - PCIUSB
  - Table 6-41. PCIUSB: USB PCI Configuration Registers
  - 282Table 6-41. PCIUSB: USB PCI Configuration Registers (Continued)
  - 283Table 6-42. USB_BAR+Memory Offset: USB Controller Registers
  - 2936.4.7 ISA Legacy Register Space
  - Table 6-43. DMA Channel Control Registers
  - 298Table 6-44. DMA Page Registers
  - 299Table 6-45. Programmable Interval Timer Registers
  - 300Table 6-45. Programmable Interval Timer Registers (Continued)
  - 301Table 6-46. Programmable Interrupt Controller Registers
  - 303Table 6-46. Programmable Interrupt Controller Registers (Continued)
  - 304Table 6-47. Keyboard Controller Registers
  - 305Table 6-48. Real-Time Clock Registers
  - Table 6-49. Miscellaneous Registers
  - 306Table 6-49. Miscellaneous Registers (Continued)
3077.0Video Processor Module
- 3087.1 Module Architecture
  - Figure 7-1. Video Processor Block Diagram
- 3097.2 Functional Description
  - 310Figure 7-2. NTSC 525 Lines, 60 Hz, Odd Field
  - Figure 7-3. NTSC 525 Lines, 60 Hz, Even Field
  - Active Video
  - 3117.2.1 Video Input Port (VIP)
  - VIP
  - Figure 7-4. VIP Block Diagram
  - 313Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer
  - 314Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers
  - 3157.2.2 Video Block
  - Figure 7-7. Video Block Diagram
  - 316Figure 7-8. Horizontal Downscaler Block Diagram
  - 3187.2.3 Mixer/Blender Block
  - Figure 7-10. Mixer/Blender Block Diagram
  - 319Table 7-1. Valid Mixing/Blending Configurations
  - 320Figure 7-11. Graphics/Video Frame with Alpha Windows
  - 321Table 7-2. Truth Table for Alpha Blending
  - 322Figure 7-12. Color Key and Alpha Blending Logic
  - 3237.2.4 VESA DDSC2B and DPMS Support
  - 7.2.5 Integrated DACs
  - Figure 7-13. DAC Voltage Levels
  - 3247.2.6 TFT Interface
  - Figure 7-14. TFT Power Sequence
  - 3257.2.7 Integrated PLL
  - Figure 7-15. PLL Block Diagram
- 3267.3 Register Descriptions
  - 7.3.1 Register Summary
  - Table 7-3. F4: PCI Header Registers for Video Processor Support Summary
  - Table 7-4. F4BAR0: Video Processor Configuration Registers Summary
  - 327Table 7-4. F4BAR0: Video Processor Configuration Registers Summary (Continued)
  - 328Table 7-5. F4BAR2: VIP Support Registers Summary
  - 3297.3.2 Video Processor Registers - Function 4
  - Table 7-6. F4: PCI Header Registers for Video Processor Support Registers
  - 331Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers
    - are located. Table 7-8 shows the memory mapped VIP sup- port registers accessed through F4BAR2.
  - 345Table 7-8. F4BAR2+Memory Offset: VIP Configuration Registers
3498.0Debugging and Monitoring
- 8.1 Testability (JTAG)
  - 8.1.1 Mandatory Instruction Support
  - 8.1.2 Optional Instruction Support
  - 8.1.3 JTAG Chain
  - Table 8-1. JTAG Mode Instruction Support
3519.0Electrical Specifications
- 9.1 General Specifications
  - 9.1.1 Electro Static Discharge (ESD)
  - 9.1.2 Power/Ground Connections and Decoupling
  - 9.1.3 Absolute Maximum Ratings
  - Table 9-1. Electro Static Discharge (ESD)
  - Table 9-2. Absolute Maximum Ratings
  - 3529.1.4 Operating Conditions
  - Table 9-3. Operating Conditions
  - 3539.1.5 DC Current
  - Table 9-4. Power Planes of External Interface Signals
  - 354Table 9-5. System Conditions Used to Measure SC2200 Current During the On State
  - Table 9-6. DC Characteristics for On State
  - 355Table 9-6. DC Characteristics for On State (Continued)
  - Table 9-7. DC Characteristics for Active Idle, Sleep, and Off States
  - 3569.1.6 Ball Capacitance and Inductance
  - Table 9-8. Ball Capacitance and Inductance
  - 3579.1.7 Pull-Up and Pull-Down Resistors
  - Table 9-9. Balls with PU/PD Resistors
- 3589.2 DC Characteristics
  - Table 9-10. Buffer Types
  - 3599.2.1 INAB DC Characteristics
  - 9.2.2 INBTN DC Characteristics
  - 9.2.3 INPCI DC Characteristics
  - 3609.2.4 INSTRP DC Characteristics
  - 9.2.5 INT DC Characteristics
  - 9.2.7 INTS1 DC Characteristics
  - 9.2.6 INTS DC Characteristics
  - 3619.2.8 INUSB DC Characteristics
  - Figure 9-1. Differential Input Sensitivity for Common Mode Range 9.2.9 OAC97 DC Characteristics
  - 9.2.10 ODn DC Characteristics
  - 3629.2.11 ODPCI DC Characteristics 9.2.12 Op/n DC Characteristics
  - 9.2.13 OPCI DC Characteristics
  - 9.2.14 OUSB DC Characteristics
  - 9.2.15 TSp/n DC Characteristics
- 3639.3 AC Characteristics
  - Figure 9-2. General Drive level and Measurement Points
  - Table 9-11. Default Levels for Measurement of Switching Parameters
  - 3649.3.1 Memory Controller Interface
  - Figure 9-3. Drive Level and Measurement Points
  - 365Table 9-12. Memory Controller Timing Parameters
  - 366Figure 9-4. Memory Controller Output Valid Timing Diagram
  - Figure 9-5. Read Data In Setup and Hold Timing Diagram
  - 9.3.2 Video Port
  - Figure 9-6. Video Input Port Timing Diagram
  - Table 9-13. Video Input Port Timing Parameters
  - 367t PCK_FR t t
  - t
  - V
    - 3689.3.3 CRT and TFT Interface
    - Figure 9-7. TFT Timing Diagram
    - Table 9-14. TFT Timing Parameters
    - 369Table 9-15. CRT VESA Compatible DAC (RED, GREEN, and BLUE Outputs)
    - 3709.3.4 ACCESS.bus Interface
    - Table 9-16. ACCESS.bus Input Timing Parameters
    - Table 9-17. ACCESS.bus Output Timing Parameters
    - 371Figure 9-8. ACB Signals: Rising Time and Falling Timing Diagram
    - Figure 9-9. ACB Start and Stop Condition Timing Diagram
    - Table 9-17. ACCESS.bus Output Timing Parameters (Continued)
    - 372Figure 9-10. ACB Start Condition Timing Diagram
    - Figure 9-11. ACB Data Bit Timing Diagram
    - 3739.3.5 PCI Bus Interface
    - Figure 9-12. Testing Setup for Slew Rate and Minimum Timing
    - Table 9-18. PCI AC Specifications
    - 374Figure 9-13. V/I Curves for PCI Output Signals
    - 375Figure 9-14. PCICLK Timing and Measurement Points
    - Table 9-19. PCI Clock Parameters
    - 376Figure 9-15. Load Circuits for Maximum Time Measurements
    - Table 9-20. PCI Timing Parameters
    - 377Figure 9-16. Output Timing Measurement Conditions
    - Table 9-21. Measurement Condition Parameters
    - 378Figure 9-17. Input Timing Measurement Conditions
    - Figure 9-18. PCI Reset Timing
    - 3799.3.6 Sub-ISA Interface
    - Table 9-22. Sub-ISA Timing Parameters
    - 380Table 9-22. Sub-ISA Timing Parameters (Continued)
    - 381Figure 9-19. Sub-ISA Read Operation Timing Diagram
    - 382Figure 9-20. Sub -ISA Write Operation Timing Diagram
    - 3839.3.7 LPC Interface
    - Figure 9-21. LPC Output Timing Diagram
    - Figure 9-22. LPC Input Timing Diagram
    - Table 9-23. LPC and SERIRQ Timing Parameters
    - 3849.3.8 IDE Interface
    - Figure 9-23. IDE Reset Timing Diagram
    - Table 9-24. IDE General Timing Parameters
    - 385Table 9-25. IDE Register Transfer to/from Device Timing Parameters
    - 386Figure 9-24. Register Transfer to/from Device Timing Diagram
    - 387Table 9-26. IDE PIO Data Transfer to/from Device Timing Parameters
    - 388Figure 9-25. PIO Data Transfer to/from Device Timing Diagram
    - 389Table 9-27. IDE Multiword DMA Data Transfer Timing Parameters
    - 390Figure 9-26. Multiword DMA Data Transfer Timing Diagram
    - 391Table 9-28. IDE UltraDMA Data Burst Timing Parameters
    - 392Figure 9-27. Initiating an UltraDMA Data in Burst Timing Diagram
    - 393Figure 9-28. Sustained UltraDMA Data In Burst Timing Diagram
    - 394Figure 9-29. Host Pausing an UltraDMA Data In Burst Timing Diagram
    - 395Figure 9-30. Device Terminating an UltraDMA Data In Burst Timing Diagram
    - 396Figure 9-31. Host Terminating an UltraDMA Data In Burst Timing Diagram
    - 397Figure 9-32. Initiating an UltraDMA Data Out Burst Timing Diagram
    - 398Figure 9-33. Sustained UltraDMA Data Out Burst Timing Diagram
    - 399Figure 9-34. Device Pausing an UltraDMA Data Out Burst Timing Diagram
    - 400Figure 9-35. Host Terminating an UltraDMA Data Out Burst Timing Diagram
    - 401Figure 9-36. Device Terminating an UltraDMA Data Out Burst Timing Diagram
    - 4029.3.9 Universal Serial Bus (USB) Interface Table 9-29. USB Timing Parameters
    - 403Table 9-29. USB Timing Parameters (Continued)
    - 404Figure 9-37. Data Signal Rise and Fall Timing Diagram
    - Figure 9-38. Source Differential Data Jitter Timing Diagram
      - N*t
      - _
      - + t
    - 405Figure 9-39. EOP Width Timing Diagram
    - Figure 9-40. Receiver Jitter Tolerance Timing Diagram
    - 4069.3.10 Serial Port (UART)
    - Figure 9-41. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram
    - Table 9-30. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Parameters
    - t
    - 4079.3.11 Fast IR Port
    - Figure 9-42. Fast IR (MIR and FIR) Timing Diagram
    - Table 9-31. Fast IR Port Timing Parameters
    - 4089.3.12 Parallel Port Interface
    - Figure 9-43. Standard Parallel Port Typical Data Exchange Timing Diagram
    - Table 9-32. Standard Parallel Port Timing Parameters
    - 409Figure 9-44. Enhanced Parallel Port Timing Diagram
    - Table 9-33. Enhanced Parallel Port Timing Parameters
    - 410Figure 9-45. ECP Forward Mode Timing Diagram
    - Table 9-34. ECP Forward Mode Timing Parameters
    - 411Figure 9-46. ECP Reverse Mode Timing Diagram
    - Table 9-35. ECP Reverse Mode Timing Parameters
    - 4129.3.13 Audio Interface (AC97)
    - Figure 9-47. AC97 Reset Timing Diagram
    - Figure 9-48. AC97 Sync Timing Diagram
    - Table 9-36. AC Reset Timing Parameters
    - Table 9-37. AC97 Sync Timing Parameters
    - 413Figure 9-49. AC97 Clocks Diagram
    - Table 9-38. AC97 Clocks Parameters
    - 414Figure 9-50. AC97 Data TIming Diagram
    - Table 9-39. AC97 I/O Timing Parameters
    - t t
    - 415Figure 9-51. AC97 Rise and Fall Timing Diagram
    - Table 9-40. AC97 Signal Rise and Fall Timing Parameters
    - 416Figure 9-52. AC97 Low Power Mode Timing Diagram
    - Table 9-41. AC97 Low Power Mode Timing Parameters
    - 4179.3.14 Power Management
    - Figure 9-53. PWRBTN# Trigger and ONCTL# Timing Diagram
    - Figure 9-54. GPWIO a nd ONCTL# Timing Diagram
    - Table 9-42. PWRBTN# Timing Parameters
    - Table 9-43. Power Management Event (GPWIO) and ONCTL# Tim ing Parameters
    - 4189.3.15 Power-Up Sequencing
    - Figure 9-55. Power-Up Sequencing With PWRBTN# Timing Diagram
    - Table 9-44. Power-Up Sequence Using the Power Button Timing Parameters
    - 419Figure 9-56. Power-Up Sequencing Without PWRBTN# Timing Diagram
    - Table 9-45. Power-Up Sequence Not Using the Power Button Timing Parameters
    - 4209.3.16 JTAG Interface
    - Figure 9-57. TCK Measurement Points and Timing Diagram
    - Table 9-46. JTAG Timing Parameters
    - 421Figure 9-58. JTAG Test Timing Diagram
42310.0Package Specifications
- 10.1 Thermal Characteristics
  - Table 10-1. JC (C/W)
  - Table 10-2. Case-to-Ambient Thermal Resistance Example @ 85C
  - 10.1.1 Heatsink Considerations
  - Figure 10-1. Heatsink Example
- 424
427Appendix ASupport Documentation
- A.1 Order Information
- 428A.2 Data Book Revision History
  - Table A-1. Revision History

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