Signal Definitions

32580B

 

 

3.4.9IDE Interface Signals

Signal Name

Ball No.

Type

Description

Mux

 

 

 

 

 

IDE_RST#

AA1

O

IDE Reset. This signal resets all the devices that are

TFTDCK

 

 

 

attached to the IDE interface.

 

 

 

 

 

 

IDE_ADDR2

U2

O

IDE Address Bits. These address bits are used to

TFTD4

 

 

 

access a register or data port in a device on the IDE bus.

 

IDE_ADDR1

AE1

 

TFTD2

 

 

 

 

 

 

 

IDE_ADDR0

AD3

 

 

TFTD3

 

 

 

 

 

IDE_DATA[15:0]

See

I/O

IDE Data Lines. IDE_DATA[15:0] transfers data to/from

The IDE interface is

 

Table 3-3

 

the IDE devices.

muxed with the TFT

 

on page

 

 

interface. See Table

 

41.

 

 

3-5 on page 46 for

 

 

 

 

details.

 

 

 

 

 

IDE_IOR0#

Y4

O

IDE I/O Read Channels 0 and 1. IDE_IOR0# is the read

TFTD10

 

 

 

signal for Channel 0 and IDE_IOR1# is the read signal

 

IDE_IOR1#

D28

O

GPIO6+DTR2#/

for Channel 1. Each signal is asserted at read accesses

 

 

 

BOUT2+SDTEST5

 

 

 

to the corresponding IDE port addresses.

 

 

 

 

 

 

 

 

 

IDE_IOW0#

AD2

O

IDE I/O Write Channels 0 and 1. IDE_IOW0# is the

TFTD9

 

 

 

write signal for Channel 0. IDE_IOW1# is the write signal

 

IDE_IOW1#

C28

O

GPIO9+DCD2#+

for Channel 1. Each signal is asserted at write accesses

 

 

 

SDTEST2

 

 

 

to corresponding IDE port addresses.

 

 

 

 

 

 

 

 

 

IDE_CS0#

AF2

O

IDE Chip Selects 0 and 1. These signals are used to

TFTD5

 

 

 

select the command block registers in an IDE device.

 

IDE_CS1#

P2

O

TFTDE

 

 

 

 

 

 

IDE_IORDY0

AD1

I

I/O Ready Channels 0 and 1. When de-asserted, these

TFTD11

 

 

 

signals extend the transfer cycle of any host register

 

IDE_IORDY1

B29

I

GPIO10+DSR2#+

access if the required device is not ready to respond to

 

 

 

SDTEST1

 

 

 

the data transfer request.

 

 

 

 

 

 

 

Note: If selected as IDE_IORDY0 or IDE_IORDY1

 

 

 

 

function(s) but not used, then signal(s) should be

 

 

 

 

tied high.

 

 

 

 

 

 

IDE_DREQ0

AC4

I

DMA Request Channels 0 and 1. The IDE_DREQ sig-

TFTD8

 

 

 

nals are used to request a DMA transfer from the

 

IDE_DREQ1

C31

I

GPIO8+CTS2#

SC2200. The direction of transfer is determined by the

 

 

 

+SDTEST4

 

 

 

IDE_IOR/IOW signals.

 

 

 

 

 

 

 

Note: If selected as IDE_DREQ0/ IDE_DREQ1 func-

 

 

 

 

tion but not used, tie IDE_DREQ0/IDE_DREQ1

 

 

 

 

low.

 

 

 

 

 

 

IDE_DACK0#

AD4

O

DMA Acknowledge Channels 0 and 1. The

TFTD0

 

 

 

IDE_DACK# signals acknowledge the DREQ request to

 

IDE_DACK1#

C30

O

GPIO7+RTS2#

initiate DMA transfers.

 

 

 

+SDTEST0

 

 

 

 

 

 

 

 

 

IRQ14

AF1

I

Interrupt Request Channels 0 and 1. These input sig-

TFTD1

 

 

 

nals are edge-sensitive interrupts that indicate when the

 

IRQ15

AJ8

I

GPIO11+RI2#

IDE device is requesting a CPU interrupt service.

 

 

 

 

 

 

 

Note: If selected as IRQ14/IRQ15 function but not

 

 

 

 

used, tie IRQ14/IRQ15 low.

 

 

 

 

 

 

AMD Geode™ SC2200 Processor Data Book

63

Page 59
Image 59
AMD SC2200 manual IDE Interface Signals