IDE Controller Registers Function, Reset Value 0502h | AMD SC2200

32580B

Core Logic Module - IDE Controller Registers - Function 2

6.4.3IDE Controller Registers - Function 2

The register space designated as Function 2 (F2) is used to configure Channels 0 and 1 and the PCI portion of sup- port hardware for the IDE controllers. The bit formats for the PCI Header/Channels 0 and 1 Registers are given in Table 6-35.

Located in the PCI Header Registers of F2 is a Base Address Register (F2BAR4) used for pointing to the regis- ter space designated for support of the IDE controllers, described later in this section.

Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration

Bit	Description

Index 00h-01h			Vendor Identification Register (RO)	Reset Value: 100Bh

Index 02h-03h			Device Identification Register (RO)	Reset Value: 0502h

Index 04h-05h			PCI Command Register (R/W)	Reset Value: 0000h

15:3	Reserved. (Read Only)

2	Bus Master. Allow the Core Logic module bus mastering capabilities.
	0:	Disable.
	1:	Enable. (Default)
	This bit must be set to 1.

1	Reserved. (Read Only)

0	I/O Space. Allow the Core Logic module to respond to I/O cycles from the PCI bus.
	0:	Disable.
	1:	Enable.
	This bit must be enabled, in order to access I/O offsets through F2BAR4 (for more information see F2 Index 20h).

Index 06h-07h			PCI Status Register (RO)	Reset Value: 0280h

Index 08h			Device Revision ID Register (RO)	Reset Value: 01h

Index 09h-0Bh			PCI Class Code Register (RO)	Reset Value: 010180h

Index 0Ch			PCI Cache Line Size Register (RO)	Reset Value: 00h

Index 0Dh			PCI Latency Timer Register (RO)	Reset Value: 00h

Index 0Eh			PCI Header Type (RO)	Reset Value: 00h

Index 0Fh			PCI BIST Register (RO)	Reset Value: 00h

Index 10h-13h			Base Address Register 0 - F2BAR0 (RO)	Reset Value: 00000000h
Reserved. Reserved for possible future use by the Core Logic module.

Index 14h-17h			Base Address Register 1 - F2BAR1 (RO)	Reset Value: 00000000h
Reserved. Reserved for possible future use by the Core Logic module.

Index 18h-1Bh			Base Address Register 2 - F2BAR2 (RO)	Reset Value: 00000000h
Reserved. Reserved for possible future use by the Core Logic module.

Index 1Ch-1Fh			Base Address Register 3 - F2BAR3 (RO)	Reset Value: 00000000h
Reserved. Reserved for possible future use by the Core Logic module.

Index 20h-23h			Base Address Register 4 - F2BAR4 (R/W)	Reset Value: 00000001h
Base Address 0 Register. This register allows access to I/O mapped Bus Mastering IDE registers. Bits [3:0] are read only (0001), indi-
cating a 16-byte I/O address range. Refer to Table 6-36 on page 270 for the IDE controller register bit formats and reset values.

31:4	Bus Mastering IDE Base Address.

3:0	Address Range. (Read Only)

Index 24h-2Bh			Reserved	Reset Value: 00h

Index 2Ch-2Dh			Subsystem Vendor ID (RO)	Reset Value: 100Bh

Index 2Eh-2Fh			Subsystem ID (RO)	Reset Value: 0502h

Index 30h-3Fh			Reserved	Reset Value: 00h


266				AMD Geode™ SC2200 Processor Data Book

Image 254

AMD SC2200 IDE Controller Registers Function, Reset Value 0502h, Reset Value 010180h, Bus Mastering IDE Base Address, 266

Contents

Publication ID 32580B AMD Geode SC2200 Processor Data Book Advanced Micro Devices, Inc. All rights reserved Contacts Trademarks Contents Core Logic Module Electrical SpecificationsPackage Specifications Video Processor Module Typical Battery Current Normal Operation Mode Power Supply ConnectionsTypical Battery Configuration ACCESS.bus Data Transaction Enhanced Parallel Port Timing Diagram 430 Multiword DMA Data Transfer Timing Diagram 411Fast IR MIR and FIR Timing Diagram 428 325 433 431432 434 32580B Relevant RTC Configuration Registers SIO Control and Configuration Register MapSIO Control and Configuration Registers RTC Configuration Registers 126 124Banks 0 and 1 Common Control and Status Registers 125 174 F2BAR4+I/O Offset IDE Controller Configuration Registers Pciusb USB PCI Configuration Register SummaryF0BAR0+I/O Offset Gpio Configuration Registers F3 PCI Header Registers for Audio Configuration PLL3 Core Logic General DescriptionVideo Processor SuperI/O GX1 Processor Module FeaturesGeneral Features Video Processor Module SuperI/O Module Other FeaturesNand Eeprom Overview 32580B Video Processor Module GX1 ModuleMemory Controller Architecture Overview 32580B SC2200 Memory Controller Registers Width Memory Offset Bits Type Name/Function Reset ValueSC2200 Memory Controller Register Summary MCMEMCNTRL2 R/W Rsvd Reserved. Write as 0070h Bit Description GXBASE+8408h-840BhMcbankcfg R/W Rsvd Reserved. Write as GXBASE+840Ch-840Fh Mcdracc R/W Mcgbaseadd R/WMcdradd R/W 1 GX1 Module Interface Fast-PCI BusDisplay Video Input Port Other Interfaces of the Core Logic Module Power-On Reset Clock, Timers, and Reset LogicReset Logic System Reset AMD Geode Signal Definitions 32580BCRT Interface IDE/TFT Interface SC2200 USB Jtag Interface Mnemonic Definition Signal Definitions LegendBall Assignments AMD Geode Configuration BGU481 Ball Assignment Sorted by Ball Number RD# Slct Buffer1 Power Signal Name VPD7 AD8 Inpci PWR AD0 Inpci AA4 IDEDATA5 MA9 AL8 SDATAIN2 BGU481 Ball Assignment Sorted Alphabetically by Signal Name Signal Name Ball No B20 FC/BE3# C17U31 C30 C11 MD27 AC30MD28 AE31 MD29 AD29 J29 F31J30 J28 Strap Options Nominal External PU/PD Strap SettingsStrap Options Default Alternate Ball No Signal Configuration Multiplexing ConfigurationTwo-Signal/Group Multiplexing TFT, CRT, PCI, GPIO, System AC97 Fpci Monitoring ACCESS.busInternal Test Three-Signal/Group Multiplexing TEST3 Four-Signal/Group MultiplexingGxclk Fpvddon Maximum Core Clock Multiplier. These strap signals Signal DescriptionsSignal Name Ball No Type Description Mux Boot ROM is 16 Bits Wide. This strap signal enables AG3 AJ2AJ3 AH2 Memory Interface Signals Column Address Strobe. RAS#, CAS#, WE# and CKE Video Port Interface Signals 4 CRT/TFT Interface Signals ACCESS.bus Interface Signals ACCESS.bus 2 Serial Data. This is the bidirectional PCI Bus Interface SignalsACCESS.bus 1 Serial Data. This is the bidirectional Multiplexed Command and Byte Enables. During IRDY# PARPERR# FRAME# TRDY# DEVSEL# STOP#LOCK# BHE# REQ1# PERR#SERR# REQ0# Sub-ISA Interface Signals Low Pin Count LPC Bus Interface Signals IDE Interface Signals Universal Serial Bus USB Interface Signals Serial Ports UARTs Interface Signals GPIO9+IDEIOW1# GPIO11+IRQ15DCD2# +SDTEST2 Parallel Port Interface Signals FFRAME# Fast Infrared IR Port Interface SignalsSTB#/WRITE# IRRX1 AK8 General Purpose Wakeup I/Os. These signals each 14 AC97 Audio Interface SignalsPower Management Interface Signals Serial Bus Synchronization. This bit is asserted to syn PWRCNT1 AK6 Suspend Power Plane Control 1 and 2. Control signalPWRBTN# AH5 PWRCNT2 AL7 Gpio Interface Signals Fast-PCI Bus Monitoring Signals. When enabled, this Debug Monitoring Interface SignalsJtag Interface Signals System Management Interrupt. This is the input to Test and Measurement Interface Signals Power, Ground and No Connections1 3V Analog USB Power Connection. Low noise power 3V PLL2 Analog Power Connection. Low noise power for PLL23V PLL3 Analog Power Connection. Low noise power for PLL3 3V Analog CRT DAC Power Connections. Low noise power 32580B General Configuration Block 32580B Configuration Block AddressesGeneral Configuration Block Register Summary Width Offset Bits PMR27 Ball # Internal Test Signals Name Add’l DependenciesOther Signal Add’l Dependencies Fpcimon General Configuration Block Ball # IDE Signals CRT, Gpio and TFT Signals Name TFT Name Add’l Dependencies BitPP/ACB1/FPCI Ball # Gpio Signals LPC Signals Name Add’l Dependencies Rsvd Reserved. Write to 32580BGeneral Configuration Block Reserved Bit Description Offset 39h-3Bh Interrupt Selection Register Intsel R/W Reset Value 00hReset Value xxh Offset 3Ch Watchdog Timer Functional Description 3describes the Watchdog registers Watchdog RegistersWatchdog Interrupt Usage Hints Offset 05h-07h Reserved Rsvd High-Resolution TimerHigh-Resolution Timer Registers Tmen Timer Interrupt Enable Reset Value xxxxxxxxhTmclksel Timer Clock Select Bit Description Offset 08h-0Bh Clock Generators and PLLs Component Parameters Values Tolerance 1 27 MHz Crystal OscillatorCrystal Oscillator Circuit Components Core Clock Frequency 2 GX1 Module Core ClockInternal Fast-PCI Clock Strapped Core Clock Frequency Video Processor Clocks SuperI/O ClocksCore Logic Module Clocks 9describes the registers of the clock generator and PLL Clock Generator ConfigurationClock Registers 33.3 MHz 15141110 66.7 MHz AB1C AB1D AB2C AB2D Outstanding FeaturesISA Serial Port PC98 and Acpi CompliantParallel Port Serial Port 3 / Infrared IR Communication Port Internal Internal Signals AccessSignals Module Architecture Index-Data Register Pair Configuration Structure/AccessSIO Configuration Options LDN Assignments Default Configuration Setup Address Decoding Logical Device Control and Configuration Registers Standard Configuration RegistersSIO Control and Configuration Registers Standard Logical Device Configuration Registers Standard Configuration Registers DMA Channel Select 1 R/W Index F0h-FEh Logical Device Configuration R/W32580BSuperI/O Module 102 Index Type Name Power Rail Reset Value SIO Control and Configuration RegistersSIO Control and Configuration Register Map SID. SIO ID Logical Device Control and Configuration Relevant RTC Configuration Registers RTC Configuration Registers Base Address MSB register Relevant SWC RegistersLDN 01h System Wakeup Control 10. IRCP/SP3 Configuration Register Relevant IRCP/SP3 Registers 11. Relevant Serial Ports 1 and 2 Registers 12. Serial Ports 1 and 2 Configuration RegisterSerial Ports 1 and 2 Configuration register LDN 03h and 08h Serial Ports 1 ACB1 and ACB2 Configuration register 14. ACB1 and ACB2 Configuration RegisterLDN 05h and 06h ACCESS.bus Ports 1 13. Relevant ACB1 and ACB2 Registers 16. Parallel Port Configuration Register 15. Relevant Parallel Port Registers Bus Interface X32I External X32O Battery = 0.1 μFReal-Time Clock RTC RTC Clock Generation Oscillator Startup Signal ParametersExternal Elements External Oscillator Daylight Saving AlarmsTimekeeping Data Format Leap Years BT1 Power SupplyRTC 18. System Power States Bit CRC Battery-Backed RAMs and RegistersInterrupt Handling 116 20. RTC Registers RTC Registers19. RTC Register Map Index Type Name CRD is Hours Register HOR R/W Reset Type VPP PURIndex 05h Hours Alarm Register Hora R/W 118 Index Programmable Century Register CEN R/W Index Programmable Month Alarm Register Mona R/WIndex 0Ch RTC Control Register C CRC RO AMD Geode SC2200 Processor Data Book 119 23. BCD and Binary Formats 21. Divider Chain Control / Test Selection22. Periodic Interrupt Rate Encoding Parameter BCD Format Binary Format RTC General-Purpose RAM Map 24. Standard RAM Map 0Eh 7Fh Battery-backed general-purpose Byte RAM00h 7Fh Battery-backed general-purpose Byte RAM 25. Extended RAM Map 26. Time Range Limits for Ceir Protocols System Wakeup Control SWCEvent Detection Type Name Value SWC Registers27. Banks 0 and 1 Common Control and Status Register Map Offset Type Name Value 29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Ceir Pulse Change, Range 1, High Limit Bit Description Ceir Wakeup Range 1 RegistersBank 1, Offset 0Ah IRWTR1L Register R/W Ceir Wakeup Range 2 Registers ABD ABC ACCESS.bus InterfaceData Transactions AMD Geode SC2200 Processor Data Book 127 ABC ACK Acknowledge ACK CycleABD MSB Arbitration on the Bus Master ModeAcknowledge After Every Byte Rule Addressing Transfer Formats Master Receive Sending the Address ByteMaster Transmit Master Stop Slave Mode Configuration 32. ACB Registers ACB Registers31. ACB Register Map MASTER. RO EN Enable Inten Interrupt EnableSaen Slave Address Enable Stop Stop 33. Parallel Port Register Map for First Level Offset Legacy Functional BlocksParallel Port 34. Parallel Port Register Map for Second Level Offset 136 35. Parallel Port Bit Map for First Level Offset36. Parallel Port Bit Map for Second Level Offset Uart Functionality SP1 and SP2 Type Name 40. Bank 2 Register Map 38. Bank Selection Encoding39. Bank 1 Register Map BSR Bits Bank Selected MRID. Module and Revision ID 41. Bank 3 Register Map42. Bank 0 Bit Map SHLCR. Shadow of LCR 45. Bank 3 Bit Map 43. Bank 1 Bit Map44. Bank 2 Bit Map Register Bits Offset 01h Register Throughout Offset 00h All Banks 3.1 IR/SP3 Mode Register Bank OverviewIRCP/SP3 Register and Bit Maps 49. Bank 2 Register Map 47. Bank Selection Encoding48. Bank 1 Register Map BSR Bits Bank Selected Functionality 52. Bank 5 Register Map 50. Bank 3 Register Map51. Bank 4 Register Map 55. Bank 0 Bit Map 53. Bank 6 Register Map54. Bank 7 Register Map 58. Bank 3 Bit Map 56. Bank 1 Bit Map57. Bank 2 Bit Map 59. Bank 4 Bit Map 62. Bank 7 Bit Map 60. Bank 5 Bit Map61. Bank 6 Bit Map Feature List Video Processor Interface ConfigIntegrated Audio Low Pin Count LPC Interface Fast-PCI Interface to External PCI Bus Pserial Interface IDE Controller IDE Configuration RegistersPIO Mode Video Retrace Interrupt Physical Region Descriptor Format Stop UltraDMA/33 Signal DefinitionsUltraDMA/33 Mode DMARDY# Strobe Ideiordy IOCS0#/IOCS1# Universal Serial BusSub-ISA Bus Interface Docw Fast-PCICLK Sub-ISA Support of Delayed PCI TransactionsSub-ISA Bus Cycles AD310 Read AD310 Write FRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR# 5.4 I/O Recovery DelaysREQ# GNT# Sub-ISA Bus Data Steering AD310 ISA DMASD150 158 ROM Interface PCI and Sub-ISA Signal Cycle MultiplexingCycle Multiplexed PCI / Sub-ISA Balls PCI DMA Controller FRAME# TRDY#, IRDY#ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP# DMA Channels DMA Transfer Types DMA Transfer ModesDMA Controller Registers DMA Priority DMA Page Registers and Extended Addressing Programmable Interval TimerDMA Addressing Capability DMA Address Generation Master PIC Interrupt MappingProgrammable Interrupt Controller Mapping PIC Shadow Register PIC Interrupt SequencePIC I/O Registers PCI Compatible Interrupts 7.1 I/O Port 092h System Control Fast Keyboard Gate Address 20 and CPU ResetKeyboard Support 7.2 I/O Port 061h System Control Power Management Logic Wakeup Events Capability Power Management Events Power Planes Control Signals vs Sleep StatesPower Planes vs. Sleep/Global States Thermal Monitoring Power ButtonPower Button Override AMD Geode SC2200 Processor Data Book 169 APM Support Power Management ProgrammingCPU Power Management Suspend Modulation AMD Geode SC2200 Processor Data Book 171 Volt SuspendSave-to-Disk General Purpose Timers Peripheral Power ManagementDevice Idle Timers and Traps Acpi Timer Register F1BAR0+I/O Power Management SMI Status Reporting RegistersModule Located at F0 Index xxh Unless Otherwise Noted Device Power Management Programming SummaryPower Management Programming Summary F1BAR0+I/O Gpio Interface Integrated Audio Audio Data Buffer 11. Physical Region Descriptor FormatByte Size PRD1 PRD2 PRD3 AMD Geode SC2200 Processor VSA Technology Trap SMI Enable RegisterVSA Technology Support Hardware Audio SMI Related Registers Module Core Logic Module Internal IRQ Control Register IRQ Configuration RegistersInternal IRQ Enable Register LPC Interface 12. Cycle Types Register Descriptions PCI Configuration Space and Access Methods13. PCI Configuration Address Register 0CF8h Mats are found Ter’s reset values and page references where the bit forRegister Summary Width Reset Reference F0 Index Bits AMD Geode SC2200 Processor Data Book 185 32580BCore Logic Module Register Summary 186 F0BAR0+ 15. F0BAR0 Gpio Support Registers Summary16. F0BAR1 LPC Support Registers Summary F0BAR1+ 18. F1BAR0 SMI Status Registers Summary F1BAR0+ 00h-03h Pcnt Processor Control Register 19. F1BAR1 Acpi Support Registers SummaryF1BAR1+ 20h PM2CNT PM2 Control Register 00h 21h-FFh Not Used Width Reset Reference F2 Index Bits 190 22. F3 PCI Header Registers for Audio Support Summary Width Reset Reference F3 Index Bits21. F2BAR4 IDE Controller Support Registers Summary F2BAR4+ F3BAR0+ Width Reset23. F3BAR0 Audio Support Registers Summary 192 F5BAR0+ Width Reset Reference F5 Index Bits25. F5BAR0 I/O Control Support Registers Summary AMD Geode SC2200 Processor Data Book 193 Pciusb 26. Pciusb USB PCI Configuration Register SummaryName Reset Value Width Reference Index Bits AMD Geode SC2200 Processor Data Book 195 27. Usbbar USB Controller Registers SummaryUSBBAR0 196 28. ISA Legacy I/O Register SummaryDMA Page Registers Table Programmable Interrupt Controller Registers Table Programmable Interval Timer Registers TablePort Type Name Reference Keyboard Controller Registers Table General Remarks Chipset Register SpaceBridge, GPIO, and LPC Registers Function Data Parity Detected. This bit is set when Core Logic Module Bridge, GPIO, and LPC Registers FunctionIndex 06h-07h PCI Status Register R/W AMD Geode SC2200 Processor Data Book 199 Index 09h-0Bh Index 0Eh PCI Header Type RO Reset Value 80hBit Description Index 08h Index 0Ch AMD Geode SC2200 Processor Data Book 201 Index 43h Reset Control Register R/W Reset Value 01hIndex 42h 202 AMD Geode SC2200 Processor Data Book 203 PIT Software Reset Reset Value FFFFFFFFhReset Value 7Bh PIT Counter 1 Enable ROM/AT Logic Control Register R/W Reset Value 98h Generate SMI on A20M# Toggle Index 5Bh Decode Control Register 2 R/W 206 INTA# Ball D26 Target Interrupt Index 5ChINTB# Ball C26 Target Interrupt Index 5Dh Chip Select 1 Positive Decode IOCS1# Reset Value 0000hIndex 72h 208 O Chip Select 0 Positive Decode IOCS0# Index 74h-75hIndex 76h IOCS0# Control Register R/W Index 77h Index 81h Power Management Enable Register 2 R/W 210 AMD Geode SC2200 Processor Data Book 211 212 Index 82h Power Management Enable Register 3 R/WKeyboard/Mouse Access Trap Primary Hard Disk Access Trap Parallel/Serial Access TrapFloppy Disk Access Trap Index 83h Power Management Enable Register 4 R/W Index 84h Second Level PME/SMI Status Mirror Register 1 RO 214 AMD Geode SC2200 Processor Data Book 215 216 AMD Geode SC2200 Processor Data Book 217 Index 88h General Purpose Timer 1 Count Register R/WReserved. Always reads 218 Re-trigger General Purpose Timer 1 on Floppy Disk ActivitySecond Millisecond AMD Geode SC2200 Processor Data Book 219 Index 8Bh General Purpose Timer 2 Control Register R/WIndex 8Dh Video Speedup Timer Count Register R/W Index 94h-95h Index 8Fh-92hIndex 93h Index 96h Index 98h-99h Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/WIndex 97h AMD Geode SC2200 Processor Data Book 221 Index A8h-A9h Video Overflow Count Register R/W Index A6h-A7h Video Idle Timer Count Register R/WIndex AAh-ABh Reserved Reset Value 00h 222 Index B0h-B3h Index AEh CPU Suspend Command Register WOIndex AFh Suspend Notebook Command Register WO Index B4h 224 Index B9h PIC Shadow Register ROIndex BAh PIT Shadow Register RO Index BDh-BFh Index BCh Clock Stop Control Register R/W Reset Value 00hReserved. Set to CPU Clock Stop Index C0h-C3h Index CEh Bit Description MaskIndex CDh Index CFh AMD Geode SC2200 Processor Data Book 227 Second Level PME/SMI Status Register 1 RC Reset Value 00hIndex F5h Second Level PME/SMI Status Register 2 RC 228 Index F6h Second Level PME/SMI Status Register 3 RCReserved . Reads as AMD Geode SC2200 Processor Data Book 229 Index F7h Second Level PME/SMI Status Register 4 RCReserved. Read as Reserved Reset Value 00h 230 F0 Index 10h, Base Address Register 0 F0BAR0 points to 30. F0BAR0+I/O Offset Gpio Configuration RegistersGpio Support Registers 232 F0BAR0+I/O Offset 18h is set, this edge generates a PME316 Reserved. Must be set to 010011 = GPIO19 ball C9 000100 Bank010010 = GPIO18 ball AG1 000011 010100 = GPIO20 balls A9, N31 000101 234 3121 31. F0BAR1+I/O Offset LPC Interface Configuration RegistersLPC Support Registers Reserved. Set to 236 Polarity selection AMD Geode SC2200 Processor Data Book 237 Number of IRQ Data Frames Reserved Serial IRQ EnableSerial IRQ Interface Mode 238 AMD Geode SC2200 Processor Data Book 239 LPC Floppy Disk Controller Address Select. Selects I/O Port LPC Game Port 1 Address Select. Selects I/O PortLPC Game Port 0 Address Select. Selects I/O Port LPC Midi Address Select. Selects I/O Port AMD Geode SC2200 Processor Data Book 241 Offset 20h-23h Lpcerradd LPC Error Address Register RO LPC Error Address 242 SMI Status and Acpi Registers Function 32. F1 PCI Header Registers for SMI Status and Acpi Support 246 33. F1BAR0+I/O Offset SMI Status RegistersSMI Status Support Registers AMD Geode SC2200 Processor Data Book 247 Suspend Modulation Enable Mirror. Read to ClearOffset 02h-03h Top Level PME/SMI Status Register RO/RC 248 Bit Description Offset 04h-05h Yes To enable SMI generation, set F0 Index 82h6 =Yes To enable SMI generation, set F0 Index 82h5 = AMD Geode SC2200 Processor Data Book 249 These addresses should not be written Offset 1Ch-1Fh Offset 08h-09h SMI Speedup Disable Register Read to EnableOffset 0Ah-1Bh 250 AMD Geode SC2200 Processor Data Book 251 Bit Description Offset 20h-21hOffset 22h-23h Second Level Acpi PME/SMI Status Register RC Offset 24h-27h External SMI Register R/W 252 Second level SMI status is reported at bits 22 RC and 14 RO Top level SMI status is reported at F1BAR0+00h/02h10Second level SMI status is reported at bits 23 RC and 15 RO Second level SMI status is reported at bits 21 RC and 13 RO 254 Offset 28h-4Fh Not UsedOffset 50h-FFh Acpi Support Registers Offset 06h Smicmd OS/BIOS Requests Register R/W34. F1BAR1+I/O Offset Acpi Support Registers Clkval Clock Throttling Value. CPU duty cycle SCI generation is always enabled 256 AMD Geode SC2200 Processor Data Book 257 Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W1511 Reserved 258 AMD Geode SC2200 Processor Data Book 259 260 Reserved AMD Geode SC2200 Processor Data Book 261 Those selected GPIOs for generation of an SCIOffset 15h Gpwio Control Register 2 R/W 262 Gpwio Data Register R/W Reset Value 00h3117 AMD Geode SC2200 Processor Data Book 263 Offset 21h-FFhRead value for these registers is undefined IDE Controller Registers Function Reset Value 0502hReset Value 010180h 314 Bus Mastering IDE Base Address AMD Geode SC2200 Processor Data Book 267 PIOMODE. PIO modeCore Logic Module IDE Controller Registers Function Index 48h-4Bh Reset Value 00009172hReset Value 00077771h 268 Index 60h-FFh Bit Description Index 50h-53hIndex 58h-5Bh AMD Geode SC2200 Processor Data Book 269 IDE Controller Support Registers 270 Offset 0Bh Offset 09hOffset 0Ah Offset 0Ch-0Fh 37. F3 PCI Header Registers for Audio Configuration Audio Registers Function Core Logic Module Audio Registers Function 38. F3BAR0+Memory Offset Audio Configuration RegistersAudio Support Registers Offset 04h-07h 274 AMD Geode SC2200 Processor Data Book 275 Offset 14h-17h Trap SMI and Fast Write Status Register RO/RC 276 AMD Geode SC2200 Processor Data Book 277 278 Mask Internal IRQ11. Write Only Mask Internal IRQ15. Write OnlyMask Internal IRQ14. Write Only Mask Internal IRQ10. Write Only Assert Masked Internal IRQ14 Mask Internal IRQ4. Write OnlyMask Internal IRQ3. Write Only Reserved. Set to Assert Masked Internal IRQ12 Bit Description Assert Masked Internal IRQ1 AMD Geode SC2200 Processor Data Book 281 Offset 2Ah-2Bh Audio Bus Master 1 Command Register R/W Reset Value 00hOffset 29h Audio Bus Master 1 SMI Status Register RC Offset 2Ch-2Fh Offset 32h-33h Audio Bus Master 2 Command Register R/W Reset Value 00hOffset 31h Audio Bus Master 2 SMI Status Register RC Offset 34h-37h Offset 3Ah-3Bh Audio Bus Master 3 Command Register R/W Reset Value 00hOffset 39h Audio Bus Master 3 SMI Status Register RC Offset 3Ch-3Fh Offset 42h-43h Audio Bus Master 4 Command Register R/W Reset Value 00hOffset 41h Audio Bus Master 4 SMI Status Register RC Offset 44h-47h Offset 4Ah-4Bh Audio Bus Master 5 Command Register R/W Reset Value 00hOffset 49h Audio Bus Master 5 SMI Status Register RC Offset 4Ch-4Fh Bus Expansion Interface Function 39. F5 PCI Header Registers for X-Bus Expansion Index 24h-27h Bit Description Index 1Ch-1FhIndex 20h-23h Index 28h-2Bh Index 4Ch-4Fh F5BAR3 Mask Address Register R/W Index 58h F5BARx Initialized Register R/W Reset Value 00hIndex 48h-4Bh F5BAR2 Mask Address Register R/W Index 50h-53h F5BAR4 Mask Address Register R/W 40. F5BAR0+I/O Offset X-Bus Expansion Registers Iotestporten Debug Test Port Enable Three USB transceivers. Default = 128USB transceivers. Default = Iostrapidselselect Idsel Strap Override 292 41. Pciusb USB PCI Configuration RegistersUSB Controller Registers Pciusb Core Logic Module USB Controller Registers Pciusb Reset Value 08hIndex 0Dh Latency Timer Register R/W Bit Description Index 06h-07h Status Register R/W Reset Value 50h Reset Value 0E11hReset Value A0F8h Bit Description Index 10h-13h AMD Geode SC2200 Processor Data Book 295 42. USBBAR+Memory Offset USB Controller RegistersCore Logic Module USB Controller Registers Pciusb 32580B RootHubStatusChangeEnable HcInterruptEnable Register R/W Reset Value = 00000000hOwnershipChangeEnable FrameNumberOverflowEnable Offset 28h-2Bh Ignore Disable interrupt generation due to Resume DetectedIgnore Disable interrupt generation due to Start of Frame 297 Bit Description Offset 34h-37h Reset Value = 00000628hReset Value = 01000003h Offset 38h-3Bh 3018 Read LocalPowerStatusChange. Not supported. Always readOffset 50h-53h HcRhStatus Register R/W AMD Geode SC2200 Processor Data Book 299 Read PortSuspendStatus HcRhPortStatus1 Register R/W Reset Value = 00000000hRead PortResetStatus 300 AMD Geode SC2200 Processor Data Book AMD Geode SC2200 Processor Data Book 301 Read PortEnableStatusRead CurrentConnectStatus 302 Offset 100h-103h Reset Value = xxhOffset 60h-9Fh 319 Reserved. Read/Write 0s 304 ISA Legacy Register Space 43. DMA Channel Control Registers 32580BCore Logic Module ISA Legacy Register Space Priority ModeTiming Mode Write Bit Description Port 00Bh Transfer ModeChannel Number Mode Select Address Direction 308 Write DMA Command Register, ChannelsUndefined Port 0D6h Bit Description Port 0D2hPort 0D4h Port 0D8h 44. DMA Page Registers 45. Programmable Interval Timer Registers Counter Value Read Current Counter Mode BCD ModeBit Description Port 042h Write Port 043h R/W 46. Programmable Interrupt Controller Registers Bit Description IRQ2 / IRQ10 Mask Poll CommandRegister Read Mode IRQ1 / IRQ9 Mask IRQ5 / IRQ13 In-Service Interrupt Service Register IRQ7 / IRQ15 In-ServiceIRQ6 / IRQ14 In-Service IRQ4 / IRQ12 In-Service 47. Keyboard Controller Registers 48. Real-Time Clock Registers 49. Miscellaneous Registers Bit Description Hardware Video Acceleration General FeaturesVideo Input Port VIP Graphics-Video Overlay and Blending 320 VIPMixer/Blender VBI Support Functional DescriptionVideo Support Video Processor Module Active Video GenLock 1.1 Direct Video ModeVideo Input Port VIP Program the VIP bus master address registers Capture Video ModeBob Program other VIP bus master support registers AMD Geode SC2200 Processor Data Book 325 WeaveAddress not changed during runtime 326 Field Interrupt Capture VBI ModePing-pongs between the two buffers during runtime Line Buffer Video BlockVideo Input Formatter AMD Geode SC2200 Processor Data Book 327 Horizontal Downscaler Horizontal Downscaler with 4-Tap FilteringFiltering 2.5 2-Tap Vertical and Horizontal Upscalers Line BuffersFormatter Ai,j Ai,j+1 Ai+1,jAi+1,j+1 RAM Mixer/Blender BlockRGB YUV Gamma Correction Valid Mixing/Blending ConfigurationsYUV to RGB CSC in Video Data Path Color/Chroma Key Video Window Color/Chroma Key and Mixer/BlenderGraphics Window Cursor Window Color Truth Table for Alpha BlendingMixing/Blending Operation CHROMASEL1 334 Monitor Vesa DDSC2B and Dpms SupportIntegrated DACs AMD Geode SC2200 Processor Data Book 335 HSYNC, VSYNC, TFTDE, Tftdck Power SequenceTFT Interface T1 is a programmable multiple of frame time T0+T1 Compare Pump Filter Divider Out Divider Phase Charge LoopIntegrated PLL AMD Geode SC2200 Processor Data Book 337 F4 PCI Header Registers for Video Processor Support Summary F4BAR0 Video Processor Configuration Registers SummaryWidth Reset Reference F4 Index Bits F4BAR0+ Video Processor Module Register Summary AMD Geode SC2200 Processor Data Book 339 F4BAR2+ F4BAR2 VIP Support Registers Summary32580BVideo Processor Module Register Summary 340 Video Processor Registers Function Reset Value 0504hReset Value 030000h Video Processor Module Video Processor Registers Function Index 3Eh-FFh Reserved 342 F4 Index 10h, Base Address Register 0 F4BAR0 sets Base address that allows PCI access to the Video ProcesVideo Processor Support Registers F4BAR0 3028 Offset 04h-07h Display Configuration Register R/WTions of the power sequence control lines 1614 Ddcsdaout DDC Output Data. DDC data bit for output Offset 08h-0Bh Video X Position Register R/W AMD Geode SC2200 Processor Data Book 345 Bit Description 100 346 Bit Description Offset 1Ch-1Fh Reset Value 00001400h12 PLL2PWREN PLL2 Power-Down Enable Block Offset 20h-23h FLTCO4 Filter Coefficient 4. For the tap-4 filter DTS Downscale Type SelectOffset 40h-43h Video Downscaler Coefficient Register R/W FLTCO3 Filter Coefficient 3. For the tap-3 filter Reset Value 00060000h Reserved Signen Signature EnableReset Value 0000xxxxh Bit Description Offset 44h-47h CRC Signature Register R/W 100 i.e., shift one line otherwise, leave at Top line is in even field. Default Top line is in odd fieldCursor Color Key Register R/W Reset Value 00000000h 350 3125 Incoming graphics stream to be ignoredOffset 60h-63h Alpha Window 1 X Position Register R/W Reserved AMD Geode SC2200 Processor Data Book 351 Reserved 352 3118Decremented until it is reloaded via bit 17 Loadalpha Reserved AMD Geode SC2200 Processor Data Book 353 Offset 400h-403h Offset 90h-93hOffset 94h-97h Video Fifo Underflow Empty Offset 404h-407h Reserved. Set to Genlocktouten GenLock Timeout EnableCtgenlocken Enable Continuous GenLock Function Offset 408h-40Bh F4BAR0+Memory Offset Video Processor Configuration Registers F4 Index 18h, Base Address Register 2 F4BAR2 points to F4BAR2+Memory Offset VIP Configuration RegistersVIP Support Registers F4BAR2 AMD Geode SC2200 Processor Data Book 357 Reserved. Read Only Current Field. Read Only Capture Store to Memory VBI DataCapture Store to Memory Video Data 2322 3110 Reserved Bit Description Video Data Capture Active. Read OnlyReserved. Read Only Run Status. Read Only Start of each field Offset 14h-17h Offset 44h-47h VBI Data Even Base Register R/W Offset 48h-4Bh VBI Data Pitch Register R/W Mandatory Instruction Support Jtag Mode Instruction SupportTestability Jtag Optional Instruction Support 366 Electro Static Discharge ESD General SpecificationsPower/Ground Connections and Decoupling Absolute Maximum Ratings Multipliers 233 or 266 MHz 300 MHz Symbol Parameter Min Typ Max Unit CommentsOperating Conditions Itor to VSS 233 or 266 MHz 300 MHz Power State Parameter Definitions Power Planes of External Interface SignalsPower Plane Signal Names VCC Balls VSS Balls DC Current DC Characteristics for On State DC Characteristics for Active Idle, Sleep, and Off States Symbol ParameterNote Min Typ Max Unit Comments Symbol Parameter Min Typ Max Unit Comment Ball Capacitance and Inductance VIO Pull-Up and Pull-Down ResistorsBalls with PU/PD Resistors External PU or PD resistor Wire DC CharacteristicsSymbol Description Reference 10. Buffer Types Inpci DC Characteristics Inab DC CharacteristicsInbtn DC Characteristics Ints DC Characteristics Instrp DC CharacteristicsINT DC Characteristics INTS1 DC Characteristics Inusb DC Characteristics ODn DC Characteristics Opci DC Characteristics Odpci DC CharacteristicsN DC Characteristics Ousb DC Characteristics Symbol Parameter Value AC Characteristics11. Default Levels for Measurement Switching Parameters CLK Inputs Memory Controller InterfaceOutputs 13.5 12. Memory Controller Timing ParametersSDCLK30, Sdclkout high time 233 MHz 266 MHz 300 MHz 12.5 BA10, MD630 T1, t2, t3SDCLK30 Control Output, MA120 MD630 Data Valid Read Data Video Port 13. Video Input Port Timing Parameters Vpckin Vref CRT and TFT Interface 14. TFT Timing Parameters Symbol Parameter Note Min Max Unit Comments 15. CRT Vesa Compatible DAC RED, GREEN, and Blue Outputs 16. ACCESS.bus Input Timing Parameters 17. ACCESS.bus Output Timing Parameters AB1C AB2C AB1CAB1D AB2D 390 AB1D AB2D AB1C AB2CAB1D AB2D AB1C 18. PCI AC Specifications PCI Bus Interface Equation a Equation B 16VIO64VIO 19. PCI Clock Parameters Pciclk 0.4 V IO 20. PCI Timing Parameters Measurement and Test Conditions Symbol Value Unit Comments21. Measurement Condition Parameters Input Valid PowerSignals Ms typ 22. Sub-ISA Timing Parameters Symbol Parameter Bits Type CommentsSub-ISA Interface Bus Width Min Bus Width Min Max Symbol Parameter Bits Type Comments DOCR#/IOR# MEMR#/DOCR# ROMCS#/DOCCS#IOR#/RD#/TRDE# IOW#/WR# MEMW#/DOCW# IOW#/WR# MEMW#/DOCW# TRDE# DOCCS#/ROMCS#IOCS10# D150 LPC Interface 23. LPC and Serirq Timing Parameters IDE Interface 24. IDE General Timing Parameters IDE signals fall time from 0.9V IO to 0.1V IO = 40 pFIDE signals rise time from 0.1V IO to 0.9V IO = 40 pF IDERST# pulse width Cycle time min Mode Symbol Parameter Unit Comments25. IDE Register Transfer to/from Device Timing Parameters Width 8-bit min Read IDEDATA70 Addr valid1IDEIOR0# IDEIOW0# Write IDEDATA70 IDEIORDY0 2,3 AMD Geode SC2200 Processor Data Book 405 26. IDE PIO Data Transfer to/from Device Timing Parameters165 125 100 406 IDEIOR0# IDEIOW0# Write IDEDATA150Read IDEDATA150 27. IDE Multiword DMA Data Transfer Timing Parameters 408 IDECS10#IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0# AMD Geode SC2200 Processor Data Book 409 Mode Symbol Parameter Min Max Unit Comments28. IDE UltraDMA Data Burst Timing Parameters IDEIOR0# HDMARDY0# IDEREQ0STOP0 IDEIRDY0 DSTROBE0 IDEDATA150 at host IDEIRDY0 DSTROBE0 at deviceIDEDATA150 at device IDEIRDY0 DSTROBE0 at host AMD Geode SC2200 Processor Data Book 411 IDEIOR0#HDMARDY0# IDEDREQ0 device IDEDACK0# hostIDEIOW0#STOP0 host 412 AMD Geode SC2200 Processor Data Book 413 IDEDREQ0 deviceIDEIOW0# STOP0# IDECS01# IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# hostIDEIRDY0 DSTROBE0 device IDEDATA150 device IDEADDR20 IDEIORDY0 DDMARDY0 device DevicetUI IDEDACK0# hostIDEIOW0# STOP0# host IDEIOR0# HSTROBE0# host IDEDATA150 At host IDEIOR0# HSTROBE0# at device HSTROBE0#At host IDEDATA150 at device IDEIOR0# HSTROBE0# IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# hostIDEIORDY0# DDMARDY0# AMD Geode SC2200 Processor Data Book 417 IDEDACK0# host IDEIORDY0# DDMARDY0# deviceIDEDATA150 host IDEADDR20 IDECS01# 418 AMD Geode SC2200 Processor Data Book 419 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# hostIDEDATA150 host IDECS01# IDEADDR20 Full Speed Receiver EOP Width Note Low Speed Source Note Receiver data jitter tolerance for paired Source EOP widthHost upstream Low Speed Receiver EOP Width Note Differential Data Lines Crossover Points 2.0 Rise Time Fall TimeDifferential Data Lines Consecutive Transitions EOP Width Differential Data to SE0 SkewData Crossover Level Consecutive Transitio ns SIR signal pulse width Modulation signal periodTCPN + Transmitter Sharp-IR and Consumer Remote Control Setting of the Rxhsc bit bit 5 of the Rccfg register FIR Fast IR Port 31. Fast IR Port Timing ParametersMIR Busy ACK# STB# Unit Comments Symbol Parameter Min33. Enhanced Parallel Port Timing Parameters AFD# 34. ECP Forward Mode Timing ParametersExtended Capabilities Port ECP Busy 35. ECP Reverse Mode Timing Parameters BUSY# Sync inactive to Bitclk startup 162.8 Delay Audio Interface AC97 36. AC Reset Timing ParametersAC97RST# inactive to Bitclk 162.8 Startup delay AC97RST# active low pulse width 38. AC97 Clocks Parameters AC97CLK Vold 39. AC97 I/O Timing Parameters SDATAOUT/SYNC SDATAIN, SDATAIN2 40. AC97 Signal Rise and Fall Timing Parameters Slot 41. AC97 Low Power Mode Timing ParametersEnd of Slot 2 to Bitclk Sdatain low Bitclk Sdataout 42. PWRBTN# Timing Parameters Power ManagementPower management event to ONCTL# Assertion ONCTL# PWRBTN# PWRBTN# ONTCL# PWRCNT21 POR# POR# 32KHZ AMD Geode SC2200 Processor Data Book 437 Jtag Interface 46. Jtag Timing Parameters TDI, TMS setup timeNon-test inputs setup time TDI, TMS hold time TDI TMS TDO Output SignalsInput Signals AMD Geode SC2200 Processor Data Book 439 440 Case-to-Ambient Thermal Resistance Example @ 85C Thermal CharacteristicsΘJC ×C/W Assume P max = 5W and TA max = 40C Therefore Heatsink ConsiderationsExample Assume P max = 9W and TA max = 40C Therefore AMD Geode SC2200 Processor Data Book 445 Physical DimensionsPackage Specifications BGU481 Package Bottom View 446 MHz Order InformationOrdering Part Number Core Frequency Degree C Package2 Revision # Revisions / Comments Data Book Revision HistoryTable A-1. Revision History