382 AMD Geodeā„¢ SC2200 Processor Data Book
Electrical Specifications
32580B
9.3.1 Memory Controller Interface
The minimum input setup and hold times described in Figure 9-3 (legend C and D) define the smallest acceptable sampling
window during which a synchronous input signal must be stable to ensure correct operation.
Figure 9-3. Drive Level and Measurement Points
SDCLK_OUT
VOH
VREF
VREF
VREF
C
Valid Output n+1
A
B
Valid Output n
OUTPUTS
INPUTS
V
IH
VIL
VOL
Min Max
Legend: A = Maximum Output Delay
B = Minimum Output Delay
C = Minimum Input Setup
D = Minimum Input Hold
D
tx
VOH
VOL
VOLD
VOHD
SDCLK_IN
VIH
VREF
VIL
tx
VILD
VIHD
SDCLK[3:0]