AMD SC2200 manual External Oscillator Connections, Divider Chain Control, Power Supply Connections

List of Figures 32580B

List of Figures

Figure 1-1.	Block Diagram	. 13
Figure 3-1.	Signal Groups	. 25
Figure 3-2.	BGU481 Ball Assignment Diagram	. 28
Figure 4-1.	WATCHDOG Block Diagram	. 83
Figure 4-2.	Clock Generation Block Diagram	. 87
Figure 4-3.	Recommended Oscillator External Circuitry	. 88
Figure 4-4.	PLL3 and Dividers Block Diagram	. 91
Figure 5-1.	SIO Block Diagram	. 95
Figure 5-2.	Detailed SIO Block Diagram	. 97
Figure 5-3.	Structure of the Standard Configuration Register File	. 98
Figure 5-4.	Standard Configuration Registers Map	100
Figure 5-5.	Recommended Oscillator External Circuitry	111
Figure 5-6.	External Oscillator Connections	112
Figure 5-7.	Divider Chain Control	112
Figure 5-8.	Power Supply Connections	114
Figure 5-9.	Typical Battery Configuration	114
Figure 5-10.	Typical Battery Current: Battery Backed Power Mode @ TC = 25°C	114
Figure 5-11.	Typical Battery Current: Normal Operation Mode	114
Figure 5-12.	Interrupt/Status Timing	116
Figure 5-13.	Bit Transfer	128
Figure 5-14.	Start and Stop Conditions	128
Figure 5-15.	ACCESS.bus Data Transaction	129
Figure 5-16.	ACCESS.bus Acknowledge Cycle	129
Figure 5-17.	A Complete ACCESS.bus Data Transaction	130
Figure 5-18.	UART Mode Register Bank Architecture	138
Figure 5-19.	IRCP/SP3 Register Bank Architecture	142
Figure 6-1.	Core Logic Module Block Diagram	150
Figure 6-2.	Non-PostedFast-PCI to ISA Access	156
Figure 6-3.	PCI to ISA Cycles with Delayed Transaction Enabled	157
Figure 6-4.	ISA DMA Read from PCI Memory	158
Figure 6-5.	ISA DMA Write to PCI Memory	158
Figure 6-6.	PCI Change to Sub-ISA and Back	160
Figure 6-7.	PIT Timer	162
Figure 6-8.	PIC Interrupt Controllers	163
Figure 6-9.	PCI and IRQ Interrupt Mapping	164
Figure 6-10.	SMI Generation for NMI	165
Figure 6-11.	General Purpose Timer and UDEF Trap SMI Tree Example	173
Figure 6-12.	PRD Table Example	177
Figure 6-13.	AC97 V2.0 Codec Signal Connections	178
Figure 6-14.	Audio SMI Tree Example	180
Figure 6-15.	Typical Setup	181
Figure 7-1.	Video Processor Block Diagram	320
Figure 7-2.	NTSC 525 Lines, 60 Hz, Odd Field	322
Figure 7-3.	NTSC 525 Lines, 60 Hz, Even Field	322
Figure 7-4.	VIP Block Diagram	323
AMD Geode™ SC2200 Processor Data Book		5