AMD SC2200 - page 204

212 AMD Geode™ SC2200 Processor Data Book
Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0
32580B
1Floppy Disk Idle Timer Enable. Turn on Floppy Disk Idle Timer Count Register (F0 Index 9Ah) and generate an SMI when
the timer expires.
0: Disable.
1: Enable.
If an access occurs in the address ranges (listed below, the timer is reloaded with the programmed count.
— Pr imary floppy disk: I/O Port 3F2h-3F5h, 3F7h.
— Secondar y floppy disk: I/O Port 372h-375h, 377h.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[1].
0Primary Hard Disk Idle Timer Enable. Turn on Primary Hard Disk Idle Timer Count Register (F0 Index 98h) and generate
an SMI when the timer expires.
0: Disable.
1: Enable.
If an access occurs in the address ranges selected in F0 Index 93h[5], the timer is reloaded with the programmed count.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[0].
Index 82h Power Management Enable Register 3 (R/W) Reset Value: 00h
7Video Access Trap. If this bit is enabled and an access occurs in the video address range (sets bit 0 of the GX1 module’s
PSERIAL register), an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[7].
6User Defined Device 3 (UDEF3) Access Trap. If this bit is enabled and an access occurs in the programmed address
range, an SMI is generated. UDEF3 address programming is at F0 Index C8h (Base Address register) and CEh (Control
register).
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[4].
5User Defined Device 2 (UDEF2) Access Trap. If this bit is enabled and an access occurs in the programmed address
range, an SMI is generated. UDEF2 address programming is at F0 Index C4h (Base Address register) and CDh (Control
register).
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[3].
4User Defined Device 1 (UDEF1) Access Trap. If this bit is enabled and an access occurs in the programmed address
range, an SMI is generated. UDEF1 address programming is at F0 Index C0h (base address register), and CCh (control
register).
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[2].
3Keyboard/Mouse Access Trap.
0: Disable.
1: Enable.
If this bit is enabled and an access occurs in the address ranges listed below, an SMI is generated.
— Keyboard Controller: I/O Ports 060h/064h.
— COM1: I/O Port 3F8h-3FFh (if F0 In dex 93h[1:0] = 10 this range is included).
— COM2: I/O Port 2F8h-2FFh (if F0 In dex 93h[1:0] = 11 this range is included).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[3].
Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit Description