Bit Description Assert Masked Internal IRQ1 | AMD SC2200 guide

Core Logic Module - Audio Registers - Function 3

32580B

Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)

Bit	Description

1	Assert Masked Internal IRQ1.
	0:	Disable.
	1:	Enable.

0	Reserved. Must be set to 0.

Offset 20h		Audio Bus Master 0 Command Register (R/W)	Reset Value: 00h
Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.

7:4	Reserved. Must be set to 0. Must return 0 on reads.

3	Read or Write Control. Sets the transfer direction of the Audio Bus Master.
	0: PCI reads are performed.
	1: PCI writes are performed.
	This bit must be set to 0 (read), and should not be changed when the bus master is active.

2:1	Reserved. Must be set to 0. Must return 0 on reads.

0	Bus Master Control. Controls the state of the Audio Bus Master.
	0:	Disable.
	1:	Enable.
	Setting this bit to 1 enables the bus master to begin data transfers.
	When writing 0 to this bit, the bus master must either be paused, or reach EOT. Writing 0 to this bit while the bus master is
	operating may result in unpredictable behavior (and may crash the bus master state machine). The only recovery from such
	unpredictable behavior is a PCI reset.

Offset 21h		Audio Bus Master 0 SMI Status Register (RC)	Reset Value: 00h
Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.

7:2	Reserved.

1	Bus Master Error. Indicates if hardware encountered a second EOP before software has cleared the first.
	0:	No.
	1:	Yes.
	If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause
	until this register is read to clear the error.

0	End of Page. Indicates if the bus master transferred data which is marked by EOP bit in the PRD table (bit 30).
	0:	No.
	1:	Yes.

Offset 22h-23h		Not Used

Offset 24h-27h		Audio Bus Master 0 PRD Table Address (R/W)	Reset Value: 00000000h
Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.

31:2	Pointer to the Physical Region Descriptor Table. This bit field contains a PRD table pointer for Audio Bus Master 0.
	When written, this register points to the first entry in a PRD table. Once Audio Bus Master 0 is enabled (Command Register
	bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next PRD.
	When read, this register points to the next PRD.

1:0	Reserved. Must be set to 0.

Note: The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from which data is to be transferred. Each entry consists of two DWORDs.

DWORD 0:	[31:0]	= Memory Region Physical Base Address
DWORD 1:	31	= End of Table Flag
	30	= End of Page Flag
	29	= Loop Flag (JMP)
	[28:16]	= Reserved (0)
	[15:0]	= Byte Count of the Region (Size)

AMD Geode™ SC2200 Processor Data Book

281

Image 269

AMD manual Bit Description Assert Masked Internal IRQ1, AMD Geode SC2200 Processor Data Book 281

Contents

AMD Geode SC2200 Processor Data Book Publication ID 32580B Contacts Trademarks Advanced Micro Devices, Inc. All rights reserved Contents Package Specifications Electrical SpecificationsCore Logic Module Video Processor Module Typical Battery Configuration Power Supply ConnectionsTypical Battery Current Normal Operation Mode ACCESS.bus Data Transaction Fast IR MIR and FIR Timing Diagram 428 Multiword DMA Data Transfer Timing Diagram 411Enhanced Parallel Port Timing Diagram 430 325 432 431433 434 32580B SIO Control and Configuration Registers SIO Control and Configuration Register MapRelevant RTC Configuration Registers RTC Configuration Registers Banks 0 and 1 Common Control and Status Registers 125 124126 174 F0BAR0+I/O Offset Gpio Configuration Registers Pciusb USB PCI Configuration Register SummaryF2BAR4+I/O Offset IDE Controller Configuration Registers F3 PCI Header Registers for Audio Configuration PLL3 Video Processor General DescriptionCore Logic SuperI/O General Features FeaturesGX1 Processor Module Video Processor Module Nand Eeprom Other FeaturesSuperI/O Module Overview 32580B Memory Controller GX1 ModuleVideo Processor Module Architecture Overview 32580B SC2200 Memory Controller Registers Width Memory Offset Bits Type Name/Function Reset ValueSC2200 Memory Controller Register Summary MCMEMCNTRL2 R/W Mcbankcfg R/W Bit Description GXBASE+8408h-840BhRsvd Reserved. Write as 0070h Rsvd Reserved. Write as GXBASE+840Ch-840Fh Mcdracc R/W Mcgbaseadd R/WMcdradd R/W Display Fast-PCI Bus1 GX1 Module Interface Video Input Port Other Interfaces of the Core Logic Module Reset Logic Clock, Timers, and Reset LogicPower-On Reset System Reset CRT Interface IDE/TFT Interface Signal Definitions 32580BAMD Geode SC2200 Jtag Interface USB Mnemonic Definition Signal Definitions LegendBall Assignments AMD Geode BGU481 Ball Assignment Sorted by Ball Number Configuration RD# Slct Buffer1 Power Signal Name VPD7 AD8 Inpci PWR AD0 Inpci AA4 IDEDATA5 MA9 AL8 SDATAIN2 Signal Name Ball No BGU481 Ball Assignment Sorted Alphabetically by Signal Name U31 FC/BE3# C17B20 C30 MD28 AE31 MD27 AC30C11 MD29 AD29 J30 F31J29 J28 Strap Options Nominal External PU/PD Strap SettingsStrap Options Two-Signal/Group Multiplexing Multiplexing ConfigurationDefault Alternate Ball No Signal Configuration TFT, CRT, PCI, GPIO, System AC97 Fpci Monitoring ACCESS.busInternal Test Three-Signal/Group Multiplexing Gxclk Four-Signal/Group MultiplexingTEST3 Fpvddon Signal Name Ball No Type Description Mux Signal DescriptionsMaximum Core Clock Multiplier. These strap signals Boot ROM is 16 Bits Wide. This strap signal enables AJ3 AJ2AG3 AH2 Column Address Strobe. RAS#, CAS#, WE# and CKE Memory Interface Signals Video Port Interface Signals ACCESS.bus Interface Signals 4 CRT/TFT Interface Signals ACCESS.bus 1 Serial Data. This is the bidirectional PCI Bus Interface SignalsACCESS.bus 2 Serial Data. This is the bidirectional Multiplexed Command and Byte Enables. During PERR# FRAME# PARIRDY# TRDY# LOCK# STOP#DEVSEL# BHE# SERR# PERR#REQ1# REQ0# Sub-ISA Interface Signals Low Pin Count LPC Bus Interface Signals IDE Interface Signals Serial Ports UARTs Interface Signals Universal Serial Bus USB Interface Signals DCD2# GPIO11+IRQ15GPIO9+IDEIOW1# +SDTEST2 Parallel Port Interface Signals STB#/WRITE# Fast Infrared IR Port Interface SignalsFFRAME# IRRX1 AK8 Power Management Interface Signals 14 AC97 Audio Interface SignalsGeneral Purpose Wakeup I/Os. These signals each Serial Bus Synchronization. This bit is asserted to syn PWRBTN# AH5 Suspend Power Plane Control 1 and 2. Control signalPWRCNT1 AK6 PWRCNT2 AL7 Gpio Interface Signals Jtag Interface Signals Debug Monitoring Interface SignalsFast-PCI Bus Monitoring Signals. When enabled, this System Management Interrupt. This is the input to Power, Ground and No Connections1 Test and Measurement Interface Signals 3V PLL3 Analog Power Connection. Low noise power for PLL3 3V PLL2 Analog Power Connection. Low noise power for PLL23V Analog USB Power Connection. Low noise power 3V Analog CRT DAC Power Connections. Low noise power 32580B General Configuration Block Register Summary Configuration Block AddressesGeneral Configuration Block 32580B Width Offset Bits Other Signal Add’l Dependencies Ball # Internal Test Signals Name Add’l DependenciesPMR27 Fpcimon Ball # IDE Signals CRT, Gpio and TFT Signals Name General Configuration Block TFT Name Add’l Dependencies BitPP/ACB1/FPCI Rsvd Reserved. Write to Ball # Gpio Signals LPC Signals Name Add’l Dependencies Reserved 32580BGeneral Configuration Block Bit Description Reset Value xxh Interrupt Selection Register Intsel R/W Reset Value 00hOffset 39h-3Bh Offset 3Ch Functional Description Watchdog Timer Watchdog Interrupt Watchdog Registers3describes the Watchdog registers Usage Hints Offset 05h-07h Reserved Rsvd High-Resolution TimerHigh-Resolution Timer Registers Tmclksel Timer Clock Select Reset Value xxxxxxxxhTmen Timer Interrupt Enable Bit Description Offset 08h-0Bh Clock Generators and PLLs Component Parameters Values Tolerance 1 27 MHz Crystal OscillatorCrystal Oscillator Circuit Components Internal Fast-PCI Clock 2 GX1 Module Core ClockCore Clock Frequency Strapped Core Clock Frequency Video Processor Clocks SuperI/O ClocksCore Logic Module Clocks 9describes the registers of the clock generator and PLL Clock Generator ConfigurationClock Registers 1110 151433.3 MHz 66.7 MHz AB1C AB1D AB2C AB2D Outstanding FeaturesISA Parallel Port PC98 and Acpi CompliantSerial Port Serial Port 3 / Infrared IR Communication Port Signals AccessInternal Internal Signals Module Architecture SIO Configuration Options Configuration Structure/AccessIndex-Data Register Pair LDN Assignments Address Decoding Default Configuration Setup SIO Control and Configuration Registers Standard Configuration RegistersLogical Device Control and Configuration Registers Standard Logical Device Configuration Registers Standard Configuration Registers 32580BSuperI/O Module Index F0h-FEh Logical Device Configuration R/WDMA Channel Select 1 R/W 102 SIO Control and Configuration Register Map SIO Control and Configuration RegistersIndex Type Name Power Rail Reset Value SID. SIO ID Relevant RTC Configuration Registers Logical Device Control and Configuration RTC Configuration Registers Base Address MSB register Relevant SWC RegistersLDN 01h System Wakeup Control Relevant IRCP/SP3 Registers 10. IRCP/SP3 Configuration Register Serial Ports 1 and 2 Configuration register 12. Serial Ports 1 and 2 Configuration Register11. Relevant Serial Ports 1 and 2 Registers LDN 03h and 08h Serial Ports 1 LDN 05h and 06h ACCESS.bus Ports 1 14. ACB1 and ACB2 Configuration RegisterACB1 and ACB2 Configuration register 13. Relevant ACB1 and ACB2 Registers 15. Relevant Parallel Port Registers 16. Parallel Port Configuration Register Real-Time Clock RTC X32I External X32O Battery = 0.1 μFBus Interface RTC Clock Generation External Elements Signal ParametersOscillator Startup External Oscillator Timekeeping Data Format AlarmsDaylight Saving Leap Years BT1 Power SupplyRTC 18. System Power States Interrupt Handling Battery-Backed RAMs and RegistersBit CRC 116 19. RTC Register Map RTC Registers20. RTC Registers Index Type Name Index 05h Hours Alarm Register Hora R/W Hours Register HOR R/W Reset Type VPP PURCRD is 118 Index 0Ch RTC Control Register C CRC RO Index Programmable Month Alarm Register Mona R/WIndex Programmable Century Register CEN R/W AMD Geode SC2200 Processor Data Book 119 22. Periodic Interrupt Rate Encoding 21. Divider Chain Control / Test Selection23. BCD and Binary Formats Parameter BCD Format Binary Format 00h 7Fh Battery-backed general-purpose Byte RAM 0Eh 7Fh Battery-backed general-purpose Byte RAMRTC General-Purpose RAM Map 24. Standard RAM Map 25. Extended RAM Map 26. Time Range Limits for Ceir Protocols System Wakeup Control SWCEvent Detection 27. Banks 0 and 1 Common Control and Status Register Map SWC RegistersType Name Value Offset Type Name Value 29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Bank 1, Offset 0Ah IRWTR1L Register R/W Bit Description Ceir Wakeup Range 1 RegistersCeir Pulse Change, Range 1, High Limit Ceir Wakeup Range 2 Registers Data Transactions ACCESS.bus InterfaceABD ABC AMD Geode SC2200 Processor Data Book 127 ABC ACK Acknowledge ACK CycleABD MSB Acknowledge After Every Byte Rule Master ModeArbitration on the Bus Addressing Transfer Formats Master Transmit Sending the Address ByteMaster Receive Master Stop Configuration Slave Mode 32. ACB Registers ACB Registers31. ACB Register Map MASTER. RO Saen Slave Address Enable Inten Interrupt EnableEN Enable Stop Stop Parallel Port Legacy Functional Blocks33. Parallel Port Register Map for First Level Offset 34. Parallel Port Register Map for Second Level Offset 136 35. Parallel Port Bit Map for First Level Offset36. Parallel Port Bit Map for Second Level Offset Type Name Uart Functionality SP1 and SP2 39. Bank 1 Register Map 38. Bank Selection Encoding40. Bank 2 Register Map BSR Bits Bank Selected 42. Bank 0 Bit Map 41. Bank 3 Register MapMRID. Module and Revision ID SHLCR. Shadow of LCR 44. Bank 2 Bit Map 43. Bank 1 Bit Map45. Bank 3 Bit Map Register Bits Offset 01h Register Throughout Offset 00h All Banks 3.1 IR/SP3 Mode Register Bank OverviewIRCP/SP3 Register and Bit Maps 48. Bank 1 Register Map 47. Bank Selection Encoding49. Bank 2 Register Map BSR Bits Bank Selected Functionality 52. Bank 5 Register Map 50. Bank 3 Register Map51. Bank 4 Register Map 55. Bank 0 Bit Map 53. Bank 6 Register Map54. Bank 7 Register Map 57. Bank 2 Bit Map 56. Bank 1 Bit Map58. Bank 3 Bit Map 59. Bank 4 Bit Map 62. Bank 7 Bit Map 60. Bank 5 Bit Map61. Bank 6 Bit Map Feature List Integrated Audio ConfigVideo Processor Interface Low Pin Count LPC Interface Pserial Interface Fast-PCI Interface to External PCI Bus PIO Mode IDE Configuration RegistersIDE Controller Video Retrace Interrupt Physical Region Descriptor Format UltraDMA/33 Mode UltraDMA/33 Signal DefinitionsStop DMARDY# Strobe Ideiordy Sub-ISA Bus Interface Universal Serial BusIOCS0#/IOCS1# Docw Sub-ISA Bus Cycles Sub-ISA Support of Delayed PCI TransactionsFast-PCICLK AD310 Read AD310 Write REQ# GNT# 5.4 I/O Recovery DelaysFRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR# Sub-ISA Bus Data Steering SD150 ISA DMAAD310 158 Cycle Multiplexed PCI / Sub-ISA Balls PCI and Sub-ISA Signal Cycle MultiplexingROM Interface PCI ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP# FRAME# TRDY#, IRDY#DMA Controller DMA Channels DMA Controller Registers DMA Transfer ModesDMA Transfer Types DMA Priority DMA Addressing Capability Programmable Interval TimerDMA Page Registers and Extended Addressing DMA Address Generation Programmable Interrupt Controller PIC Interrupt MappingMaster Mapping PIC I/O Registers PIC Interrupt SequencePIC Shadow Register PCI Compatible Interrupts Keyboard Support Fast Keyboard Gate Address 20 and CPU Reset7.1 I/O Port 092h System Control 7.2 I/O Port 061h System Control Power Management Logic Wakeup Events Capability Power Management Events Power Planes Control Signals vs Sleep StatesPower Planes vs. Sleep/Global States Power Button Override Power ButtonThermal Monitoring AMD Geode SC2200 Processor Data Book 169 CPU Power Management Power Management ProgrammingAPM Support Suspend Modulation AMD Geode SC2200 Processor Data Book 171 Volt SuspendSave-to-Disk Device Idle Timers and Traps Peripheral Power ManagementGeneral Purpose Timers Acpi Timer Register F1BAR0+I/O Power Management SMI Status Reporting RegistersModule Power Management Programming Summary Device Power Management Programming SummaryLocated at F0 Index xxh Unless Otherwise Noted F1BAR0+I/O Integrated Audio Gpio Interface Byte 11. Physical Region Descriptor FormatAudio Data Buffer Size PRD3 PRD1 PRD2 AMD Geode SC2200 Processor VSA Technology Support Hardware Trap SMI Enable RegisterVSA Technology Audio SMI Related Registers Module Core Logic Module Internal IRQ Enable Register IRQ Configuration RegistersInternal IRQ Control Register LPC Interface 12. Cycle Types Register Descriptions PCI Configuration Space and Access Methods13. PCI Configuration Address Register 0CF8h Mats are found Ter’s reset values and page references where the bit forRegister Summary AMD Geode SC2200 Processor Data Book 185 Width Reset Reference F0 Index Bits 186 32580BCore Logic Module Register Summary 16. F0BAR1 LPC Support Registers Summary 15. F0BAR0 Gpio Support Registers SummaryF0BAR0+ F0BAR1+ F1BAR0+ 18. F1BAR0 SMI Status Registers Summary F1BAR1+ 19. F1BAR1 Acpi Support Registers Summary00h-03h Pcnt Processor Control Register 20h PM2CNT PM2 Control Register 00h 21h-FFh Not Used 190 Width Reset Reference F2 Index Bits 21. F2BAR4 IDE Controller Support Registers Summary Width Reset Reference F3 Index Bits22. F3 PCI Header Registers for Audio Support Summary F2BAR4+ 23. F3BAR0 Audio Support Registers Summary Width ResetF3BAR0+ 192 25. F5BAR0 I/O Control Support Registers Summary Width Reset Reference F5 Index BitsF5BAR0+ AMD Geode SC2200 Processor Data Book 193 Name Reset Value 26. Pciusb USB PCI Configuration Register SummaryPciusb Width Reference Index Bits AMD Geode SC2200 Processor Data Book 195 27. Usbbar USB Controller Registers SummaryUSBBAR0 196 28. ISA Legacy I/O Register SummaryDMA Page Registers Table Port Type Name Reference Programmable Interval Timer Registers TableProgrammable Interrupt Controller Registers Table Keyboard Controller Registers Table General Remarks Chipset Register SpaceBridge, GPIO, and LPC Registers Function Index 06h-07h PCI Status Register R/W Core Logic Module Bridge, GPIO, and LPC Registers FunctionData Parity Detected. This bit is set when AMD Geode SC2200 Processor Data Book 199 Bit Description Index 08h Index 0Eh PCI Header Type RO Reset Value 80hIndex 09h-0Bh Index 0Ch AMD Geode SC2200 Processor Data Book 201 Index 42h Reset Control Register R/W Reset Value 01hIndex 43h 202 AMD Geode SC2200 Processor Data Book 203 Reset Value 7Bh Reset Value FFFFFFFFhPIT Software Reset PIT Counter 1 Enable Generate SMI on A20M# Toggle ROM/AT Logic Control Register R/W Reset Value 98h 206 Index 5Bh Decode Control Register 2 R/W INTB# Ball C26 Target Interrupt Index 5ChINTA# Ball D26 Target Interrupt Index 5Dh Index 72h Reset Value 0000hChip Select 1 Positive Decode IOCS1# 208 Index 76h IOCS0# Control Register R/W Index 74h-75hO Chip Select 0 Positive Decode IOCS0# Index 77h 210 Index 81h Power Management Enable Register 2 R/W AMD Geode SC2200 Processor Data Book 211 212 Index 82h Power Management Enable Register 3 R/WKeyboard/Mouse Access Trap Floppy Disk Access Trap Parallel/Serial Access TrapPrimary Hard Disk Access Trap Index 83h Power Management Enable Register 4 R/W 214 Index 84h Second Level PME/SMI Status Mirror Register 1 RO AMD Geode SC2200 Processor Data Book 215 216 AMD Geode SC2200 Processor Data Book 217 Index 88h General Purpose Timer 1 Count Register R/WReserved. Always reads 218 Re-trigger General Purpose Timer 1 on Floppy Disk ActivitySecond Millisecond AMD Geode SC2200 Processor Data Book 219 Index 8Bh General Purpose Timer 2 Control Register R/WIndex 8Dh Video Speedup Timer Count Register R/W Index 93h Index 8Fh-92hIndex 94h-95h Index 96h Index 97h Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/WIndex 98h-99h AMD Geode SC2200 Processor Data Book 221 Index A8h-A9h Video Overflow Count Register R/W Index A6h-A7h Video Idle Timer Count Register R/WIndex AAh-ABh Reserved Reset Value 00h 222 Index AFh Suspend Notebook Command Register WO Index AEh CPU Suspend Command Register WOIndex B0h-B3h Index B4h 224 Index B9h PIC Shadow Register ROIndex BAh PIT Shadow Register RO Reserved. Set to CPU Clock Stop Index BCh Clock Stop Control Register R/W Reset Value 00hIndex BDh-BFh Index C0h-C3h Index CDh Bit Description MaskIndex CEh Index CFh AMD Geode SC2200 Processor Data Book 227 Second Level PME/SMI Status Register 1 RC Reset Value 00hIndex F5h Second Level PME/SMI Status Register 2 RC 228 Index F6h Second Level PME/SMI Status Register 3 RCReserved . Reads as AMD Geode SC2200 Processor Data Book 229 Index F7h Second Level PME/SMI Status Register 4 RCReserved. Read as Reserved Reset Value 00h 230 F0 Index 10h, Base Address Register 0 F0BAR0 points to 30. F0BAR0+I/O Offset Gpio Configuration RegistersGpio Support Registers 232 F0BAR0+I/O Offset 18h is set, this edge generates a PME316 Reserved. Must be set to 010010 = GPIO18 ball AG1 000011 Bank010011 = GPIO19 ball C9 000100 010100 = GPIO20 balls A9, N31 000101 234 LPC Support Registers 31. F0BAR1+I/O Offset LPC Interface Configuration Registers3121 Reserved. Set to 236 AMD Geode SC2200 Processor Data Book 237 Polarity selection Serial IRQ Interface Mode Reserved Serial IRQ EnableNumber of IRQ Data Frames 238 AMD Geode SC2200 Processor Data Book 239 LPC Game Port 0 Address Select. Selects I/O Port LPC Game Port 1 Address Select. Selects I/O PortLPC Floppy Disk Controller Address Select. Selects I/O Port LPC Midi Address Select. Selects I/O Port AMD Geode SC2200 Processor Data Book 241 LPC Error Address 242 Offset 20h-23h Lpcerradd LPC Error Address Register RO 32. F1 PCI Header Registers for SMI Status and Acpi Support SMI Status and Acpi Registers Function 246 33. F1BAR0+I/O Offset SMI Status RegistersSMI Status Support Registers AMD Geode SC2200 Processor Data Book 247 Suspend Modulation Enable Mirror. Read to ClearOffset 02h-03h Top Level PME/SMI Status Register RO/RC 248 Yes To enable SMI generation, set F0 Index 82h5 = Yes To enable SMI generation, set F0 Index 82h6 =Bit Description Offset 04h-05h AMD Geode SC2200 Processor Data Book 249 Offset 0Ah-1Bh Offset 08h-09h SMI Speedup Disable Register Read to EnableThese addresses should not be written Offset 1Ch-1Fh 250 AMD Geode SC2200 Processor Data Book 251 Bit Description Offset 20h-21hOffset 22h-23h Second Level Acpi PME/SMI Status Register RC 252 Offset 24h-27h External SMI Register R/W Second level SMI status is reported at bits 23 RC and 15 RO Top level SMI status is reported at F1BAR0+00h/02h10Second level SMI status is reported at bits 22 RC and 14 RO Second level SMI status is reported at bits 21 RC and 13 RO 254 Offset 28h-4Fh Not UsedOffset 50h-FFh 34. F1BAR1+I/O Offset Acpi Support Registers Offset 06h Smicmd OS/BIOS Requests Register R/WAcpi Support Registers Clkval Clock Throttling Value. CPU duty cycle 256 SCI generation is always enabled AMD Geode SC2200 Processor Data Book 257 Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W1511 Reserved 258 AMD Geode SC2200 Processor Data Book 259 260 Reserved AMD Geode SC2200 Processor Data Book 261 Those selected GPIOs for generation of an SCIOffset 15h Gpwio Control Register 2 R/W 262 Gpwio Data Register R/W Reset Value 00h3117 AMD Geode SC2200 Processor Data Book 263 Offset 21h-FFhRead value for these registers is undefined Reset Value 010180h Reset Value 0502hIDE Controller Registers Function 314 Bus Mastering IDE Base Address AMD Geode SC2200 Processor Data Book 267 PIOMODE. PIO modeCore Logic Module IDE Controller Registers Function Reset Value 00077771h Reset Value 00009172hIndex 48h-4Bh 268 Index 58h-5Bh Bit Description Index 50h-53hIndex 60h-FFh AMD Geode SC2200 Processor Data Book 269 270 IDE Controller Support Registers Offset 0Ah Offset 09hOffset 0Bh Offset 0Ch-0Fh Audio Registers Function 37. F3 PCI Header Registers for Audio Configuration Audio Support Registers 38. F3BAR0+Memory Offset Audio Configuration RegistersCore Logic Module Audio Registers Function Offset 04h-07h 274 AMD Geode SC2200 Processor Data Book 275 276 Offset 14h-17h Trap SMI and Fast Write Status Register RO/RC AMD Geode SC2200 Processor Data Book 277 278 Mask Internal IRQ14. Write Only Mask Internal IRQ15. Write OnlyMask Internal IRQ11. Write Only Mask Internal IRQ10. Write Only Mask Internal IRQ3. Write Only Mask Internal IRQ4. Write OnlyAssert Masked Internal IRQ14 Reserved. Set to Assert Masked Internal IRQ12 AMD Geode SC2200 Processor Data Book 281 Bit Description Assert Masked Internal IRQ1 Offset 29h Audio Bus Master 1 SMI Status Register RC Audio Bus Master 1 Command Register R/W Reset Value 00hOffset 2Ah-2Bh Offset 2Ch-2Fh Offset 31h Audio Bus Master 2 SMI Status Register RC Audio Bus Master 2 Command Register R/W Reset Value 00hOffset 32h-33h Offset 34h-37h Offset 39h Audio Bus Master 3 SMI Status Register RC Audio Bus Master 3 Command Register R/W Reset Value 00hOffset 3Ah-3Bh Offset 3Ch-3Fh Offset 41h Audio Bus Master 4 SMI Status Register RC Audio Bus Master 4 Command Register R/W Reset Value 00hOffset 42h-43h Offset 44h-47h Offset 49h Audio Bus Master 5 SMI Status Register RC Audio Bus Master 5 Command Register R/W Reset Value 00hOffset 4Ah-4Bh Offset 4Ch-4Fh 39. F5 PCI Header Registers for X-Bus Expansion Bus Expansion Interface Function Index 20h-23h Bit Description Index 1Ch-1FhIndex 24h-27h Index 28h-2Bh Index 48h-4Bh F5BAR2 Mask Address Register R/W Index 58h F5BARx Initialized Register R/W Reset Value 00hIndex 4Ch-4Fh F5BAR3 Mask Address Register R/W Index 50h-53h F5BAR4 Mask Address Register R/W 40. F5BAR0+I/O Offset X-Bus Expansion Registers USB transceivers. Default = Three USB transceivers. Default = 128Iotestporten Debug Test Port Enable Iostrapidselselect Idsel Strap Override 292 41. Pciusb USB PCI Configuration RegistersUSB Controller Registers Pciusb Index 0Dh Latency Timer Register R/W Reset Value 08hCore Logic Module USB Controller Registers Pciusb Bit Description Index 06h-07h Status Register R/W Reset Value A0F8h Reset Value 0E11hReset Value 50h Bit Description Index 10h-13h AMD Geode SC2200 Processor Data Book 295 42. USBBAR+Memory Offset USB Controller RegistersCore Logic Module USB Controller Registers Pciusb 32580B OwnershipChangeEnable HcInterruptEnable Register R/W Reset Value = 00000000hRootHubStatusChangeEnable FrameNumberOverflowEnable Ignore Disable interrupt generation due to Start of Frame Ignore Disable interrupt generation due to Resume DetectedOffset 28h-2Bh 297 Reset Value = 01000003h Reset Value = 00000628hBit Description Offset 34h-37h Offset 38h-3Bh Offset 50h-53h HcRhStatus Register R/W Read LocalPowerStatusChange. Not supported. Always read3018 AMD Geode SC2200 Processor Data Book 299 Read PortResetStatus HcRhPortStatus1 Register R/W Reset Value = 00000000hRead PortSuspendStatus 300 AMD Geode SC2200 Processor Data Book AMD Geode SC2200 Processor Data Book 301 Read PortEnableStatusRead CurrentConnectStatus 302 Offset 60h-9Fh Reset Value = xxhOffset 100h-103h 319 Reserved. Read/Write 0s 304 43. DMA Channel Control Registers ISA Legacy Register Space Timing Mode Priority Mode32580BCore Logic Module ISA Legacy Register Space Write Channel Number Mode Select Transfer ModeBit Description Port 00Bh Address Direction 308 Write DMA Command Register, ChannelsUndefined Port 0D4h Bit Description Port 0D2hPort 0D6h Port 0D8h 44. DMA Page Registers 45. Programmable Interval Timer Registers Bit Description Port 042h Write Current Counter Mode BCD ModeCounter Value Read Port 043h R/W 46. Programmable Interrupt Controller Registers Register Read Mode Poll CommandBit Description IRQ2 / IRQ10 Mask IRQ1 / IRQ9 Mask IRQ6 / IRQ14 In-Service Interrupt Service Register IRQ7 / IRQ15 In-ServiceIRQ5 / IRQ13 In-Service IRQ4 / IRQ12 In-Service 47. Keyboard Controller Registers 49. Miscellaneous Registers 48. Real-Time Clock Registers Bit Description Video Input Port VIP General FeaturesHardware Video Acceleration Graphics-Video Overlay and Blending 320 VIPMixer/Blender Video Support Functional DescriptionVBI Support Video Processor Module Active Video GenLock 1.1 Direct Video ModeVideo Input Port VIP Bob Capture Video ModeProgram the VIP bus master address registers Program other VIP bus master support registers AMD Geode SC2200 Processor Data Book 325 WeaveAddress not changed during runtime 326 Field Interrupt Capture VBI ModePing-pongs between the two buffers during runtime Video Input Formatter Video BlockLine Buffer AMD Geode SC2200 Processor Data Book 327 Horizontal Downscaler Horizontal Downscaler with 4-Tap FilteringFiltering Formatter Line Buffers2.5 2-Tap Vertical and Horizontal Upscalers Ai,j Ai,j+1 Ai+1,jAi+1,j+1 RGB Mixer/Blender BlockRAM YUV YUV to RGB CSC in Video Data Path Valid Mixing/Blending ConfigurationsGamma Correction Color/Chroma Key Graphics Window Color/Chroma Key and Mixer/BlenderVideo Window Cursor Window Mixing/Blending Operation Truth Table for Alpha BlendingColor CHROMASEL1 334 Integrated DACs Vesa DDSC2B and Dpms SupportMonitor AMD Geode SC2200 Processor Data Book 335 TFT Interface Power SequenceHSYNC, VSYNC, TFTDE, Tftdck T1 is a programmable multiple of frame time T0+T1 Integrated PLL Divider Phase Charge LoopCompare Pump Filter Divider Out AMD Geode SC2200 Processor Data Book 337 Width Reset Reference F4 Index Bits F4BAR0 Video Processor Configuration Registers SummaryF4 PCI Header Registers for Video Processor Support Summary F4BAR0+ AMD Geode SC2200 Processor Data Book 339 Video Processor Module Register Summary 32580BVideo Processor Module Register Summary F4BAR2 VIP Support Registers SummaryF4BAR2+ 340 Reset Value 030000h Reset Value 0504hVideo Processor Registers Function Video Processor Module Video Processor Registers Function 342 Index 3Eh-FFh Reserved F4 Index 10h, Base Address Register 0 F4BAR0 sets Base address that allows PCI access to the Video ProcesVideo Processor Support Registers F4BAR0 Tions of the power sequence control lines 1614 Offset 04h-07h Display Configuration Register R/W3028 Ddcsdaout DDC Output Data. DDC data bit for output AMD Geode SC2200 Processor Data Book 345 Offset 08h-0Bh Video X Position Register R/W 346 Bit Description 100 12 PLL2PWREN PLL2 Power-Down Enable Reset Value 00001400hBit Description Offset 1Ch-1Fh Block Offset 20h-23h Offset 40h-43h Video Downscaler Coefficient Register R/W DTS Downscale Type SelectFLTCO4 Filter Coefficient 4. For the tap-4 filter FLTCO3 Filter Coefficient 3. For the tap-3 filter Reset Value 0000xxxxh Reserved Signen Signature EnableReset Value 00060000h Bit Description Offset 44h-47h CRC Signature Register R/W Cursor Color Key Register R/W Reset Value 00000000h Top line is in even field. Default Top line is in odd field100 i.e., shift one line otherwise, leave at 350 Offset 60h-63h Alpha Window 1 X Position Register R/W Incoming graphics stream to be ignored3125 Reserved AMD Geode SC2200 Processor Data Book 351 Reserved 352 3118Decremented until it is reloaded via bit 17 Loadalpha Reserved AMD Geode SC2200 Processor Data Book 353 Offset 94h-97h Offset 90h-93hOffset 400h-403h Video Fifo Underflow Empty Ctgenlocken Enable Continuous GenLock Function Reserved. Set to Genlocktouten GenLock Timeout EnableOffset 404h-407h Offset 408h-40Bh F4BAR0+Memory Offset Video Processor Configuration Registers VIP Support Registers F4BAR2 F4BAR2+Memory Offset VIP Configuration RegistersF4 Index 18h, Base Address Register 2 F4BAR2 points to AMD Geode SC2200 Processor Data Book 357 Capture Store to Memory Video Data Capture Store to Memory VBI DataReserved. Read Only Current Field. Read Only 2322 Reserved. Read Only Run Status. Read Only Bit Description Video Data Capture Active. Read Only3110 Reserved Start of each field Offset 14h-17h Offset 48h-4Bh VBI Data Pitch Register R/W Offset 44h-47h VBI Data Even Base Register R/W Testability Jtag Jtag Mode Instruction SupportMandatory Instruction Support Optional Instruction Support 366 Power/Ground Connections and Decoupling General SpecificationsElectro Static Discharge ESD Absolute Maximum Ratings Operating Conditions Symbol Parameter Min Typ Max Unit CommentsMultipliers 233 or 266 MHz 300 MHz Itor to VSS 233 or 266 MHz 300 MHz Power Plane Signal Names VCC Balls VSS Balls Power Planes of External Interface SignalsPower State Parameter Definitions DC Current DC Characteristics for On State Symbol ParameterNote Min Typ Max Unit Comments DC Characteristics for Active Idle, Sleep, and Off States Ball Capacitance and Inductance Symbol Parameter Min Typ Max Unit Comment Balls with PU/PD Resistors Pull-Up and Pull-Down ResistorsVIO External PU or PD resistor Symbol Description Reference DC CharacteristicsWire 10. Buffer Types Inpci DC Characteristics Inab DC CharacteristicsInbtn DC Characteristics INT DC Characteristics Instrp DC CharacteristicsInts DC Characteristics INTS1 DC Characteristics ODn DC Characteristics Inusb DC Characteristics N DC Characteristics Odpci DC CharacteristicsOpci DC Characteristics Ousb DC Characteristics 11. Default Levels for Measurement Switching Parameters AC CharacteristicsSymbol Parameter Value CLK Inputs Memory Controller InterfaceOutputs SDCLK30, Sdclkout high time 233 MHz 266 MHz 300 MHz 12. Memory Controller Timing Parameters13.5 12.5 SDCLK30 Control Output, MA120 T1, t2, t3BA10, MD630 MD630 Data Valid Read Data Vpckin Vref Video Port 13. Video Input Port Timing Parameters 14. TFT Timing Parameters CRT and TFT Interface 15. CRT Vesa Compatible DAC RED, GREEN, and Blue Outputs Symbol Parameter Note Min Max Unit Comments 17. ACCESS.bus Output Timing Parameters 16. ACCESS.bus Input Timing Parameters AB1C AB2C AB1CAB1D AB2D 390 AB1D AB2D AB1C AB2CAB1D AB2D AB1C PCI Bus Interface 18. PCI AC Specifications Equation a Equation B 16VIO64VIO Pciclk 0.4 V IO 19. PCI Clock Parameters 20. PCI Timing Parameters Measurement and Test Conditions Symbol Value Unit Comments21. Measurement Condition Parameters Signals PowerInput Valid Ms typ Sub-ISA Interface Symbol Parameter Bits Type Comments22. Sub-ISA Timing Parameters Bus Width Min DOCR#/IOR# Bus Width Min Max Symbol Parameter Bits Type Comments IOR#/RD#/TRDE# ROMCS#/DOCCS#MEMR#/DOCR# IOW#/WR# MEMW#/DOCW# IOCS10# DOCCS#/ROMCS#IOW#/WR# MEMW#/DOCW# TRDE# D150 LPC Interface 23. LPC and Serirq Timing Parameters IDE signals rise time from 0.1V IO to 0.9V IO = 40 pF IDE signals fall time from 0.9V IO to 0.1V IO = 40 pFIDE Interface 24. IDE General Timing Parameters IDERST# pulse width 25. IDE Register Transfer to/from Device Timing Parameters Mode Symbol Parameter Unit CommentsCycle time min Width 8-bit min IDEIOR0# IDEIOW0# Write IDEDATA70 Addr valid1Read IDEDATA70 IDEIORDY0 2,3 AMD Geode SC2200 Processor Data Book 405 26. IDE PIO Data Transfer to/from Device Timing Parameters165 125 100 406 IDEIOR0# IDEIOW0# Write IDEDATA150Read IDEDATA150 27. IDE Multiword DMA Data Transfer Timing Parameters 408 IDECS10#IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0# AMD Geode SC2200 Processor Data Book 409 Mode Symbol Parameter Min Max Unit Comments28. IDE UltraDMA Data Burst Timing Parameters STOP0 IDEREQ0IDEIOR0# HDMARDY0# IDEIRDY0 DSTROBE0 IDEDATA150 at device IDEIRDY0 DSTROBE0 at host IDEIRDY0 DSTROBE0 at deviceIDEDATA150 at host AMD Geode SC2200 Processor Data Book 411 IDEIOW0#STOP0 host IDEDREQ0 device IDEDACK0# hostIDEIOR0#HDMARDY0# 412 AMD Geode SC2200 Processor Data Book 413 IDEDREQ0 deviceIDEIOW0# STOP0# IDEIRDY0 DSTROBE0 device IDEDATA150 device IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# hostIDECS01# IDEADDR20 IDEIOW0# STOP0# host DevicetUI IDEDACK0# hostIDEIORDY0 DDMARDY0 device IDEIOR0# HSTROBE0# host At host HSTROBE0#IDEDATA150 At host IDEIOR0# HSTROBE0# at device IDEDATA150 at device IDEIORDY0# DDMARDY0# IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# hostIDEIOR0# HSTROBE0# AMD Geode SC2200 Processor Data Book 417 IDEDATA150 host IDEADDR20 IDECS01# IDEIORDY0# DDMARDY0# deviceIDEDACK0# host 418 AMD Geode SC2200 Processor Data Book 419 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# hostIDEDATA150 host IDECS01# IDEADDR20 Low Speed Source Note Full Speed Receiver EOP Width Note Host upstream Source EOP widthReceiver data jitter tolerance for paired Low Speed Receiver EOP Width Note Differential Data Lines Rise Time Fall TimeDifferential Data Lines Crossover Points 2.0 Consecutive Transitions Data Crossover Level Differential Data to SE0 SkewEOP Width Consecutive Transitio ns TCPN + Transmitter Sharp-IR and Consumer Remote Control Modulation signal periodSIR signal pulse width Setting of the Rxhsc bit bit 5 of the Rccfg register FIR Fast IR Port 31. Fast IR Port Timing ParametersMIR STB# Busy ACK# Unit Comments Symbol Parameter Min33. Enhanced Parallel Port Timing Parameters Extended Capabilities Port ECP 34. ECP Forward Mode Timing ParametersAFD# Busy BUSY# 35. ECP Reverse Mode Timing Parameters AC97RST# inactive to Bitclk 162.8 Startup delay Audio Interface AC97 36. AC Reset Timing ParametersSync inactive to Bitclk startup 162.8 Delay AC97RST# active low pulse width AC97CLK Vold 38. AC97 Clocks Parameters SDATAOUT/SYNC SDATAIN, SDATAIN2 39. AC97 I/O Timing Parameters 40. AC97 Signal Rise and Fall Timing Parameters End of Slot 2 to Bitclk Sdatain low 41. AC97 Low Power Mode Timing ParametersSlot Bitclk Sdataout Power management event to ONCTL# Assertion Power Management42. PWRBTN# Timing Parameters ONCTL# PWRBTN# PWRBTN# ONTCL# PWRCNT21 POR# AMD Geode SC2200 Processor Data Book 437 POR# 32KHZ Non-test inputs setup time TDI, TMS setup timeJtag Interface 46. Jtag Timing Parameters TDI, TMS hold time Input Signals Output SignalsTDI TMS TDO AMD Geode SC2200 Processor Data Book 439 440 Case-to-Ambient Thermal Resistance Example @ 85C Thermal CharacteristicsΘJC ×C/W Example Heatsink ConsiderationsAssume P max = 5W and TA max = 40C Therefore Assume P max = 9W and TA max = 40C Therefore AMD Geode SC2200 Processor Data Book 445 Physical DimensionsPackage Specifications 446 BGU481 Package Bottom View Ordering Part Number Core Frequency Order InformationMHz Degree C Package2 Revision # Revisions / Comments Data Book Revision HistoryTable A-1. Revision History