AMD SC2200 manual Acknowledge ACK Cycle, Abd Msb, Abc Ack

32580B SuperI/O Module

5.7.3Acknowledge (ACK) Cycle

The ACK cycle consists of two signals: the ACK clock pulse sent by the master with each byte transferred, and the ACK signal sent by the receiving device (see Figure 5-15).

The master generates the ACK clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases

ABD

MSB

the ABD line (permits it to go high) to allow the receiver to send the ACK signal. The receiver must pull down the ABD line during the ACK clock pulse, signalling that it has cor- rectly received the last data byte and is ready to receive the next byte. Figure 5-16illustrates the ACK cycle.

Acknowledge

Signal From Receiver

ABC
		1	2 3 - 6	7	8		9
	S					ACK

Start

Condition

Byte Complete

Interrupt Within

Receiver

1	2	3 - 8		9	P
			ACK

Stop Condition

Clock Line Held Low by Receiver While Interrupt is Serviced

Figure 5-15. ACCESS.bus Data Transaction

Data Output								Transmitter Stays Off Bus
by Transmitter
								During Acknowledge Clock
Data Output
								Acknowledge
by Receiver
								Signal From Receiver
ABC				3 - 6
	S	1	2		7	8	9

Start

Condition

Figure 5-16. ACCESS.bus Acknowledge Cycle

128 AMD Geode™ SC2200 Processor Data Book