33. F1BAR0+I/O Offset SMI Status Registers, 246 | AMD SC2200

32580B

Core Logic Module - SMI Status and ACPI Registers - Function 1

6.4.2.1SMI Status Support Registers

F1 Index 10h, Base Address Register 0 (F1BAR0), points to the base address for SMI Status register locations. Table 6-33gives the bit formats of I/O mapped SMI Status regis- ters accessed through F1BAR0.

The registers at F1BAR0+I/O Offset 50h-FFh can also be accessed F0 Index 50h-FFh. The preferred method is to program these registers through the F0 register space.

Table 6-33. F1BAR0+I/O Offset: SMI Status Registers

Bit		Description

Offset 00h-01h			Top Level PME/SMI Status Mirror Register (RO)	Reset Value: 0000h
Note:	Reading this register does not clear the status bits. For more information, see F1BAR0+I/O Offset 02h.

15		Suspend Modulation Enable Mirror. This bit mirrors the Suspend Mode Configuration bit (F0 Index 96h[0]). It is used by
		the SMI handler to determine if the SMI Speedup Disable Register (F1BAR0+I/O Offset 08h) must be cleared on exit.

14		SMI Source is USB. Indicates whether or not an SMI was caused by USB activity.
		0:	No.
		1:	Yes.
		To enable SMI generation, set F5BAR0+I/O Offset 00h[20:19] to 11.

13		SMI Source is Warm Reset Command. Indicates whether or not an SMI was caused by a Warm Reset command.
		0:	No.
		1:	Yes.

12		SMI Source is NMI. Indicates whether or not an SMI was caused by NMI activity.
		0:	No.
		1:	Yes.

11		SMI Source is IRQ2 of SIO Module. Indicates whether or not an SMI was caused by IRQ2 of the SIO module.
		0:	No.
		1:	Yes.
		The next level (second level) of SMI status is reported in the SuperI/O module. For more information, see Table 5-29 "Banks
		0 and 1 - Common Control and Status Registers" on page 125, Offset 00h.

10		SMI Source is EXT_SMI[7:0]. Indicates whether or not an SMI was caused by a negative-edge event on EXT_SMI[7:0].
		0:	No.
		1:	Yes.
		The next level (second level) of SMI status is at F1BAR0+I/O Offset 24h[23:8].

9		SMI Source is GP Timers/UDEF/PCI/ISA Function Trap. Indicates if an SMI was caused by:
		— Expiration of GP Timer 1 or 2.
		— Trapped access to UDEF1, 2, or 3.
		— Trapped access to F1-F5 or ISA Legacy register space.
		0:	No.
		1:	Yes.
		The next level (second level) of SMI status is at F1BAR0+I/O Offset 04h/06h.

8		SMI Source is Software Generated. Indicates whether or not an SMI was caused by software.
		0:	No.
		1:	Yes.

7		SMI on an A20M# Toggle. Indicates whether or not an SMI was caused by a write access to either Port 92h or the key-
		board command which initiates an A20M# SMI.
		0:	No.
		1:	Yes.
		This method of controlling the internal A20M# in the GX1 module is used instead of a pin.
		To enable SMI generation, set F0 Index 53h[0] to 1.

6		SMI Source is a VGA Timer Event. Indicates whether or not an SMI was caused by the expiration of the VGA Timer (F0
		Index 8Eh).
		0:	No.
		1:	Yes.
		To enable SMI generation, set F0 Index 83h[3] to 1.


246			AMD Geode™ SC2200 Processor Data Book

Image 236

AMD SC2200 manual 33. F1BAR0+I/O Offset SMI Status Registers, SMI Status Support Registers, 246

Contents

Publication ID 32580B AMD Geode SC2200 Processor Data Book Advanced Micro Devices, Inc. All rights reserved Contacts Trademarks Contents Electrical Specifications Package SpecificationsCore Logic Module Video Processor Module Power Supply Connections Typical Battery ConfigurationTypical Battery Current Normal Operation Mode ACCESS.bus Data Transaction Multiword DMA Data Transfer Timing Diagram 411 Fast IR MIR and FIR Timing Diagram 428Enhanced Parallel Port Timing Diagram 430 325 431 432433 434 32580B SIO Control and Configuration Register Map SIO Control and Configuration RegistersRelevant RTC Configuration Registers RTC Configuration Registers 124 Banks 0 and 1 Common Control and Status Registers 125126 174 Pciusb USB PCI Configuration Register Summary F0BAR0+I/O Offset Gpio Configuration RegistersF2BAR4+I/O Offset IDE Controller Configuration Registers F3 PCI Header Registers for Audio Configuration PLL3 General Description Video ProcessorCore Logic SuperI/O Features General FeaturesGX1 Processor Module Video Processor Module Other Features Nand EepromSuperI/O Module Overview 32580B GX1 Module Memory ControllerVideo Processor Module Architecture Overview 32580B SC2200 Memory Controller Registers Width Memory Offset Bits Type Name/Function Reset ValueSC2200 Memory Controller Register Summary MCMEMCNTRL2 R/W Bit Description GXBASE+8408h-840Bh Mcbankcfg R/WRsvd Reserved. Write as 0070h Rsvd Reserved. Write as GXBASE+840Ch-840Fh Mcdracc R/W Mcgbaseadd R/WMcdradd R/W Fast-PCI Bus Display1 GX1 Module Interface Video Input Port Other Interfaces of the Core Logic Module Clock, Timers, and Reset Logic Reset LogicPower-On Reset System Reset Signal Definitions 32580B CRT Interface IDE/TFT InterfaceAMD Geode SC2200 USB Jtag Interface Mnemonic Definition Signal Definitions LegendBall Assignments AMD Geode Configuration BGU481 Ball Assignment Sorted by Ball Number RD# Slct Buffer1 Power Signal Name VPD7 AD8 Inpci PWR AD0 Inpci AA4 IDEDATA5 MA9 AL8 SDATAIN2 BGU481 Ball Assignment Sorted Alphabetically by Signal Name Signal Name Ball No FC/BE3# C17 U31B20 C30 MD27 AC30 MD28 AE31C11 MD29 AD29 F31 J30J29 J28 Strap Options Nominal External PU/PD Strap SettingsStrap Options Multiplexing Configuration Two-Signal/Group MultiplexingDefault Alternate Ball No Signal Configuration TFT, CRT, PCI, GPIO, System AC97 Fpci Monitoring ACCESS.busInternal Test Three-Signal/Group Multiplexing Four-Signal/Group Multiplexing GxclkTEST3 Fpvddon Signal Descriptions Signal Name Ball No Type Description MuxMaximum Core Clock Multiplier. These strap signals Boot ROM is 16 Bits Wide. This strap signal enables AJ2 AJ3AG3 AH2 Memory Interface Signals Column Address Strobe. RAS#, CAS#, WE# and CKE Video Port Interface Signals 4 CRT/TFT Interface Signals ACCESS.bus Interface Signals PCI Bus Interface Signals ACCESS.bus 1 Serial Data. This is the bidirectionalACCESS.bus 2 Serial Data. This is the bidirectional Multiplexed Command and Byte Enables. During PAR PERR# FRAME#IRDY# TRDY# STOP# LOCK#DEVSEL# BHE# PERR# SERR#REQ1# REQ0# Sub-ISA Interface Signals Low Pin Count LPC Bus Interface Signals IDE Interface Signals Universal Serial Bus USB Interface Signals Serial Ports UARTs Interface Signals GPIO11+IRQ15 DCD2#GPIO9+IDEIOW1# +SDTEST2 Parallel Port Interface Signals Fast Infrared IR Port Interface Signals STB#/WRITE#FFRAME# IRRX1 AK8 14 AC97 Audio Interface Signals Power Management Interface SignalsGeneral Purpose Wakeup I/Os. These signals each Serial Bus Synchronization. This bit is asserted to syn Suspend Power Plane Control 1 and 2. Control signal PWRBTN# AH5PWRCNT1 AK6 PWRCNT2 AL7 Gpio Interface Signals Debug Monitoring Interface Signals Jtag Interface SignalsFast-PCI Bus Monitoring Signals. When enabled, this System Management Interrupt. This is the input to Test and Measurement Interface Signals Power, Ground and No Connections1 3V PLL2 Analog Power Connection. Low noise power for PLL2 3V PLL3 Analog Power Connection. Low noise power for PLL33V Analog USB Power Connection. Low noise power 3V Analog CRT DAC Power Connections. Low noise power 32580B Configuration Block Addresses General Configuration Block Register SummaryGeneral Configuration Block 32580B Width Offset Bits Ball # Internal Test Signals Name Add’l Dependencies Other Signal Add’l DependenciesPMR27 Fpcimon General Configuration Block Ball # IDE Signals CRT, Gpio and TFT Signals Name TFT Name Add’l Dependencies BitPP/ACB1/FPCI Ball # Gpio Signals LPC Signals Name Add’l Dependencies Rsvd Reserved. Write to 32580BGeneral Configuration Block Reserved Bit Description Interrupt Selection Register Intsel R/W Reset Value 00h Reset Value xxhOffset 39h-3Bh Offset 3Ch Watchdog Timer Functional Description Watchdog Registers Watchdog Interrupt3describes the Watchdog registers Usage Hints Offset 05h-07h Reserved Rsvd High-Resolution TimerHigh-Resolution Timer Registers Reset Value xxxxxxxxh Tmclksel Timer Clock SelectTmen Timer Interrupt Enable Bit Description Offset 08h-0Bh Clock Generators and PLLs Component Parameters Values Tolerance 1 27 MHz Crystal OscillatorCrystal Oscillator Circuit Components 2 GX1 Module Core Clock Internal Fast-PCI ClockCore Clock Frequency Strapped Core Clock Frequency Video Processor Clocks SuperI/O ClocksCore Logic Module Clocks 9describes the registers of the clock generator and PLL Clock Generator ConfigurationClock Registers 1514 111033.3 MHz 66.7 MHz AB1C AB1D AB2C AB2D Outstanding FeaturesISA PC98 and Acpi Compliant Parallel PortSerial Port Serial Port 3 / Infrared IR Communication Port Access SignalsInternal Internal Signals Module Architecture Configuration Structure/Access SIO Configuration OptionsIndex-Data Register Pair LDN Assignments Default Configuration Setup Address Decoding Standard Configuration Registers SIO Control and Configuration RegistersLogical Device Control and Configuration Registers Standard Logical Device Configuration Registers Standard Configuration Registers Index F0h-FEh Logical Device Configuration R/W 32580BSuperI/O ModuleDMA Channel Select 1 R/W 102 SIO Control and Configuration Registers SIO Control and Configuration Register MapIndex Type Name Power Rail Reset Value SID. SIO ID Logical Device Control and Configuration Relevant RTC Configuration Registers RTC Configuration Registers Base Address MSB register Relevant SWC RegistersLDN 01h System Wakeup Control 10. IRCP/SP3 Configuration Register Relevant IRCP/SP3 Registers 12. Serial Ports 1 and 2 Configuration Register Serial Ports 1 and 2 Configuration register11. Relevant Serial Ports 1 and 2 Registers LDN 03h and 08h Serial Ports 1 14. ACB1 and ACB2 Configuration Register LDN 05h and 06h ACCESS.bus Ports 1ACB1 and ACB2 Configuration register 13. Relevant ACB1 and ACB2 Registers 16. Parallel Port Configuration Register 15. Relevant Parallel Port Registers X32I External X32O Battery = 0.1 μF Real-Time Clock RTCBus Interface RTC Clock Generation Signal Parameters External ElementsOscillator Startup External Oscillator Alarms Timekeeping Data FormatDaylight Saving Leap Years BT1 Power SupplyRTC 18. System Power States Battery-Backed RAMs and Registers Interrupt HandlingBit CRC 116 RTC Registers 19. RTC Register Map20. RTC Registers Index Type Name Hours Register HOR R/W Reset Type VPP PUR Index 05h Hours Alarm Register Hora R/WCRD is 118 Index Programmable Month Alarm Register Mona R/W Index 0Ch RTC Control Register C CRC ROIndex Programmable Century Register CEN R/W AMD Geode SC2200 Processor Data Book 119 21. Divider Chain Control / Test Selection 22. Periodic Interrupt Rate Encoding23. BCD and Binary Formats Parameter BCD Format Binary Format 0Eh 7Fh Battery-backed general-purpose Byte RAM 00h 7Fh Battery-backed general-purpose Byte RAMRTC General-Purpose RAM Map 24. Standard RAM Map 25. Extended RAM Map 26. Time Range Limits for Ceir Protocols System Wakeup Control SWCEvent Detection SWC Registers 27. Banks 0 and 1 Common Control and Status Register MapType Name Value Offset Type Name Value 29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Bit Description Ceir Wakeup Range 1 Registers Bank 1, Offset 0Ah IRWTR1L Register R/WCeir Pulse Change, Range 1, High Limit Ceir Wakeup Range 2 Registers ACCESS.bus Interface Data TransactionsABD ABC AMD Geode SC2200 Processor Data Book 127 ABC ACK Acknowledge ACK CycleABD MSB Master Mode Acknowledge After Every Byte RuleArbitration on the Bus Addressing Transfer Formats Sending the Address Byte Master TransmitMaster Receive Master Stop Slave Mode Configuration 32. ACB Registers ACB Registers31. ACB Register Map MASTER. RO Inten Interrupt Enable Saen Slave Address EnableEN Enable Stop Stop Legacy Functional Blocks Parallel Port33. Parallel Port Register Map for First Level Offset 34. Parallel Port Register Map for Second Level Offset 136 35. Parallel Port Bit Map for First Level Offset36. Parallel Port Bit Map for Second Level Offset Uart Functionality SP1 and SP2 Type Name 38. Bank Selection Encoding 39. Bank 1 Register Map40. Bank 2 Register Map BSR Bits Bank Selected 41. Bank 3 Register Map 42. Bank 0 Bit MapMRID. Module and Revision ID SHLCR. Shadow of LCR 43. Bank 1 Bit Map 44. Bank 2 Bit Map45. Bank 3 Bit Map Register Bits Offset 01h Register Throughout Offset 00h All Banks 3.1 IR/SP3 Mode Register Bank OverviewIRCP/SP3 Register and Bit Maps 47. Bank Selection Encoding 48. Bank 1 Register Map49. Bank 2 Register Map BSR Bits Bank Selected Functionality 52. Bank 5 Register Map 50. Bank 3 Register Map51. Bank 4 Register Map 55. Bank 0 Bit Map 53. Bank 6 Register Map54. Bank 7 Register Map 56. Bank 1 Bit Map 57. Bank 2 Bit Map58. Bank 3 Bit Map 59. Bank 4 Bit Map 62. Bank 7 Bit Map 60. Bank 5 Bit Map61. Bank 6 Bit Map Feature List Config Integrated AudioVideo Processor Interface Low Pin Count LPC Interface Fast-PCI Interface to External PCI Bus Pserial Interface IDE Configuration Registers PIO ModeIDE Controller Video Retrace Interrupt Physical Region Descriptor Format UltraDMA/33 Signal Definitions UltraDMA/33 ModeStop DMARDY# Strobe Ideiordy Universal Serial Bus Sub-ISA Bus InterfaceIOCS0#/IOCS1# Docw Sub-ISA Support of Delayed PCI Transactions Sub-ISA Bus CyclesFast-PCICLK AD310 Read AD310 Write 5.4 I/O Recovery Delays REQ# GNT#FRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR# Sub-ISA Bus Data Steering ISA DMA SD150AD310 158 PCI and Sub-ISA Signal Cycle Multiplexing Cycle Multiplexed PCI / Sub-ISA BallsROM Interface PCI FRAME# TRDY#, IRDY# ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP#DMA Controller DMA Channels DMA Transfer Modes DMA Controller RegistersDMA Transfer Types DMA Priority Programmable Interval Timer DMA Addressing CapabilityDMA Page Registers and Extended Addressing DMA Address Generation PIC Interrupt Mapping Programmable Interrupt ControllerMaster Mapping PIC Interrupt Sequence PIC I/O RegistersPIC Shadow Register PCI Compatible Interrupts Fast Keyboard Gate Address 20 and CPU Reset Keyboard Support7.1 I/O Port 092h System Control 7.2 I/O Port 061h System Control Power Management Logic Wakeup Events Capability Power Management Events Power Planes Control Signals vs Sleep StatesPower Planes vs. Sleep/Global States Power Button Power Button OverrideThermal Monitoring AMD Geode SC2200 Processor Data Book 169 Power Management Programming CPU Power ManagementAPM Support Suspend Modulation AMD Geode SC2200 Processor Data Book 171 Volt SuspendSave-to-Disk Peripheral Power Management Device Idle Timers and TrapsGeneral Purpose Timers Acpi Timer Register F1BAR0+I/O Power Management SMI Status Reporting RegistersModule Device Power Management Programming Summary Power Management Programming SummaryLocated at F0 Index xxh Unless Otherwise Noted F1BAR0+I/O Gpio Interface Integrated Audio 11. Physical Region Descriptor Format ByteAudio Data Buffer Size PRD1 PRD2 PRD3 AMD Geode SC2200 Processor Trap SMI Enable Register VSA Technology Support HardwareVSA Technology Audio SMI Related Registers Module Core Logic Module IRQ Configuration Registers Internal IRQ Enable RegisterInternal IRQ Control Register LPC Interface 12. Cycle Types Register Descriptions PCI Configuration Space and Access Methods13. PCI Configuration Address Register 0CF8h Mats are found Ter’s reset values and page references where the bit forRegister Summary Width Reset Reference F0 Index Bits AMD Geode SC2200 Processor Data Book 185 32580BCore Logic Module Register Summary 186 15. F0BAR0 Gpio Support Registers Summary 16. F0BAR1 LPC Support Registers SummaryF0BAR0+ F0BAR1+ 18. F1BAR0 SMI Status Registers Summary F1BAR0+ 19. F1BAR1 Acpi Support Registers Summary F1BAR1+00h-03h Pcnt Processor Control Register 20h PM2CNT PM2 Control Register 00h 21h-FFh Not Used Width Reset Reference F2 Index Bits 190 Width Reset Reference F3 Index Bits 21. F2BAR4 IDE Controller Support Registers Summary22. F3 PCI Header Registers for Audio Support Summary F2BAR4+ Width Reset 23. F3BAR0 Audio Support Registers SummaryF3BAR0+ 192 Width Reset Reference F5 Index Bits 25. F5BAR0 I/O Control Support Registers SummaryF5BAR0+ AMD Geode SC2200 Processor Data Book 193 26. Pciusb USB PCI Configuration Register Summary Name Reset ValuePciusb Width Reference Index Bits AMD Geode SC2200 Processor Data Book 195 27. Usbbar USB Controller Registers SummaryUSBBAR0 196 28. ISA Legacy I/O Register SummaryDMA Page Registers Table Programmable Interval Timer Registers Table Port Type Name ReferenceProgrammable Interrupt Controller Registers Table Keyboard Controller Registers Table General Remarks Chipset Register SpaceBridge, GPIO, and LPC Registers Function Core Logic Module Bridge, GPIO, and LPC Registers Function Index 06h-07h PCI Status Register R/WData Parity Detected. This bit is set when AMD Geode SC2200 Processor Data Book 199 Index 0Eh PCI Header Type RO Reset Value 80h Bit Description Index 08hIndex 09h-0Bh Index 0Ch AMD Geode SC2200 Processor Data Book 201 Reset Control Register R/W Reset Value 01h Index 42hIndex 43h 202 AMD Geode SC2200 Processor Data Book 203 Reset Value FFFFFFFFh Reset Value 7BhPIT Software Reset PIT Counter 1 Enable ROM/AT Logic Control Register R/W Reset Value 98h Generate SMI on A20M# Toggle Index 5Bh Decode Control Register 2 R/W 206 Index 5Ch INTB# Ball C26 Target InterruptINTA# Ball D26 Target Interrupt Index 5Dh Reset Value 0000h Index 72hChip Select 1 Positive Decode IOCS1# 208 Index 74h-75h Index 76h IOCS0# Control Register R/WO Chip Select 0 Positive Decode IOCS0# Index 77h Index 81h Power Management Enable Register 2 R/W 210 AMD Geode SC2200 Processor Data Book 211 212 Index 82h Power Management Enable Register 3 R/WKeyboard/Mouse Access Trap Parallel/Serial Access Trap Floppy Disk Access TrapPrimary Hard Disk Access Trap Index 83h Power Management Enable Register 4 R/W Index 84h Second Level PME/SMI Status Mirror Register 1 RO 214 AMD Geode SC2200 Processor Data Book 215 216 AMD Geode SC2200 Processor Data Book 217 Index 88h General Purpose Timer 1 Count Register R/WReserved. Always reads 218 Re-trigger General Purpose Timer 1 on Floppy Disk ActivitySecond Millisecond AMD Geode SC2200 Processor Data Book 219 Index 8Bh General Purpose Timer 2 Control Register R/WIndex 8Dh Video Speedup Timer Count Register R/W Index 8Fh-92h Index 93hIndex 94h-95h Index 96h Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/W Index 97hIndex 98h-99h AMD Geode SC2200 Processor Data Book 221 Index A8h-A9h Video Overflow Count Register R/W Index A6h-A7h Video Idle Timer Count Register R/WIndex AAh-ABh Reserved Reset Value 00h 222 Index AEh CPU Suspend Command Register WO Index AFh Suspend Notebook Command Register WOIndex B0h-B3h Index B4h 224 Index B9h PIC Shadow Register ROIndex BAh PIT Shadow Register RO Index BCh Clock Stop Control Register R/W Reset Value 00h Reserved. Set to CPU Clock StopIndex BDh-BFh Index C0h-C3h Bit Description Mask Index CDhIndex CEh Index CFh AMD Geode SC2200 Processor Data Book 227 Second Level PME/SMI Status Register 1 RC Reset Value 00hIndex F5h Second Level PME/SMI Status Register 2 RC 228 Index F6h Second Level PME/SMI Status Register 3 RCReserved . Reads as AMD Geode SC2200 Processor Data Book 229 Index F7h Second Level PME/SMI Status Register 4 RCReserved. Read as Reserved Reset Value 00h 230 F0 Index 10h, Base Address Register 0 F0BAR0 points to 30. F0BAR0+I/O Offset Gpio Configuration RegistersGpio Support Registers 232 F0BAR0+I/O Offset 18h is set, this edge generates a PME316 Reserved. Must be set to Bank 010010 = GPIO18 ball AG1 000011010011 = GPIO19 ball C9 000100 010100 = GPIO20 balls A9, N31 000101 234 31. F0BAR1+I/O Offset LPC Interface Configuration Registers LPC Support Registers3121 Reserved. Set to 236 Polarity selection AMD Geode SC2200 Processor Data Book 237 Reserved Serial IRQ Enable Serial IRQ Interface ModeNumber of IRQ Data Frames 238 AMD Geode SC2200 Processor Data Book 239 LPC Game Port 1 Address Select. Selects I/O Port LPC Game Port 0 Address Select. Selects I/O PortLPC Floppy Disk Controller Address Select. Selects I/O Port LPC Midi Address Select. Selects I/O Port AMD Geode SC2200 Processor Data Book 241 Offset 20h-23h Lpcerradd LPC Error Address Register RO LPC Error Address 242 SMI Status and Acpi Registers Function 32. F1 PCI Header Registers for SMI Status and Acpi Support 246 33. F1BAR0+I/O Offset SMI Status RegistersSMI Status Support Registers AMD Geode SC2200 Processor Data Book 247 Suspend Modulation Enable Mirror. Read to ClearOffset 02h-03h Top Level PME/SMI Status Register RO/RC 248 Yes To enable SMI generation, set F0 Index 82h6 = Yes To enable SMI generation, set F0 Index 82h5 =Bit Description Offset 04h-05h AMD Geode SC2200 Processor Data Book 249 Offset 08h-09h SMI Speedup Disable Register Read to Enable Offset 0Ah-1BhThese addresses should not be written Offset 1Ch-1Fh 250 AMD Geode SC2200 Processor Data Book 251 Bit Description Offset 20h-21hOffset 22h-23h Second Level Acpi PME/SMI Status Register RC Offset 24h-27h External SMI Register R/W 252 Top level SMI status is reported at F1BAR0+00h/02h10 Second level SMI status is reported at bits 23 RC and 15 ROSecond level SMI status is reported at bits 22 RC and 14 RO Second level SMI status is reported at bits 21 RC and 13 RO 254 Offset 28h-4Fh Not UsedOffset 50h-FFh Offset 06h Smicmd OS/BIOS Requests Register R/W 34. F1BAR1+I/O Offset Acpi Support RegistersAcpi Support Registers Clkval Clock Throttling Value. CPU duty cycle SCI generation is always enabled 256 AMD Geode SC2200 Processor Data Book 257 Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W1511 Reserved 258 AMD Geode SC2200 Processor Data Book 259 260 Reserved AMD Geode SC2200 Processor Data Book 261 Those selected GPIOs for generation of an SCIOffset 15h Gpwio Control Register 2 R/W 262 Gpwio Data Register R/W Reset Value 00h3117 AMD Geode SC2200 Processor Data Book 263 Offset 21h-FFhRead value for these registers is undefined Reset Value 0502h Reset Value 010180hIDE Controller Registers Function 314 Bus Mastering IDE Base Address AMD Geode SC2200 Processor Data Book 267 PIOMODE. PIO modeCore Logic Module IDE Controller Registers Function Reset Value 00009172h Reset Value 00077771hIndex 48h-4Bh 268 Bit Description Index 50h-53h Index 58h-5BhIndex 60h-FFh AMD Geode SC2200 Processor Data Book 269 IDE Controller Support Registers 270 Offset 09h Offset 0AhOffset 0Bh Offset 0Ch-0Fh 37. F3 PCI Header Registers for Audio Configuration Audio Registers Function 38. F3BAR0+Memory Offset Audio Configuration Registers Audio Support RegistersCore Logic Module Audio Registers Function Offset 04h-07h 274 AMD Geode SC2200 Processor Data Book 275 Offset 14h-17h Trap SMI and Fast Write Status Register RO/RC 276 AMD Geode SC2200 Processor Data Book 277 278 Mask Internal IRQ15. Write Only Mask Internal IRQ14. Write OnlyMask Internal IRQ11. Write Only Mask Internal IRQ10. Write Only Mask Internal IRQ4. Write Only Mask Internal IRQ3. Write OnlyAssert Masked Internal IRQ14 Reserved. Set to Assert Masked Internal IRQ12 Bit Description Assert Masked Internal IRQ1 AMD Geode SC2200 Processor Data Book 281 Audio Bus Master 1 Command Register R/W Reset Value 00h Offset 29h Audio Bus Master 1 SMI Status Register RCOffset 2Ah-2Bh Offset 2Ch-2Fh Audio Bus Master 2 Command Register R/W Reset Value 00h Offset 31h Audio Bus Master 2 SMI Status Register RCOffset 32h-33h Offset 34h-37h Audio Bus Master 3 Command Register R/W Reset Value 00h Offset 39h Audio Bus Master 3 SMI Status Register RCOffset 3Ah-3Bh Offset 3Ch-3Fh Audio Bus Master 4 Command Register R/W Reset Value 00h Offset 41h Audio Bus Master 4 SMI Status Register RCOffset 42h-43h Offset 44h-47h Audio Bus Master 5 Command Register R/W Reset Value 00h Offset 49h Audio Bus Master 5 SMI Status Register RCOffset 4Ah-4Bh Offset 4Ch-4Fh Bus Expansion Interface Function 39. F5 PCI Header Registers for X-Bus Expansion Bit Description Index 1Ch-1Fh Index 20h-23hIndex 24h-27h Index 28h-2Bh Index 58h F5BARx Initialized Register R/W Reset Value 00h Index 48h-4Bh F5BAR2 Mask Address Register R/WIndex 4Ch-4Fh F5BAR3 Mask Address Register R/W Index 50h-53h F5BAR4 Mask Address Register R/W 40. F5BAR0+I/O Offset X-Bus Expansion Registers Three USB transceivers. Default = 128 USB transceivers. Default =Iotestporten Debug Test Port Enable Iostrapidselselect Idsel Strap Override 292 41. Pciusb USB PCI Configuration RegistersUSB Controller Registers Pciusb Reset Value 08h Index 0Dh Latency Timer Register R/WCore Logic Module USB Controller Registers Pciusb Bit Description Index 06h-07h Status Register R/W Reset Value 0E11h Reset Value A0F8hReset Value 50h Bit Description Index 10h-13h AMD Geode SC2200 Processor Data Book 295 42. USBBAR+Memory Offset USB Controller RegistersCore Logic Module USB Controller Registers Pciusb 32580B HcInterruptEnable Register R/W Reset Value = 00000000h OwnershipChangeEnableRootHubStatusChangeEnable FrameNumberOverflowEnable Ignore Disable interrupt generation due to Resume Detected Ignore Disable interrupt generation due to Start of FrameOffset 28h-2Bh 297 Reset Value = 00000628h Reset Value = 01000003hBit Description Offset 34h-37h Offset 38h-3Bh Read LocalPowerStatusChange. Not supported. Always read Offset 50h-53h HcRhStatus Register R/W3018 AMD Geode SC2200 Processor Data Book 299 HcRhPortStatus1 Register R/W Reset Value = 00000000h Read PortResetStatusRead PortSuspendStatus 300 AMD Geode SC2200 Processor Data Book AMD Geode SC2200 Processor Data Book 301 Read PortEnableStatusRead CurrentConnectStatus 302 Reset Value = xxh Offset 60h-9FhOffset 100h-103h 319 Reserved. Read/Write 0s 304 ISA Legacy Register Space 43. DMA Channel Control Registers Priority Mode Timing Mode32580BCore Logic Module ISA Legacy Register Space Write Transfer Mode Channel Number Mode SelectBit Description Port 00Bh Address Direction 308 Write DMA Command Register, ChannelsUndefined Bit Description Port 0D2h Port 0D4hPort 0D6h Port 0D8h 44. DMA Page Registers 45. Programmable Interval Timer Registers Current Counter Mode BCD Mode Bit Description Port 042h WriteCounter Value Read Port 043h R/W 46. Programmable Interrupt Controller Registers Poll Command Register Read ModeBit Description IRQ2 / IRQ10 Mask IRQ1 / IRQ9 Mask Interrupt Service Register IRQ7 / IRQ15 In-Service IRQ6 / IRQ14 In-ServiceIRQ5 / IRQ13 In-Service IRQ4 / IRQ12 In-Service 47. Keyboard Controller Registers 48. Real-Time Clock Registers 49. Miscellaneous Registers Bit Description General Features Video Input Port VIPHardware Video Acceleration Graphics-Video Overlay and Blending 320 VIPMixer/Blender Functional Description Video SupportVBI Support Video Processor Module Active Video GenLock 1.1 Direct Video ModeVideo Input Port VIP Capture Video Mode BobProgram the VIP bus master address registers Program other VIP bus master support registers AMD Geode SC2200 Processor Data Book 325 WeaveAddress not changed during runtime 326 Field Interrupt Capture VBI ModePing-pongs between the two buffers during runtime Video Block Video Input FormatterLine Buffer AMD Geode SC2200 Processor Data Book 327 Horizontal Downscaler Horizontal Downscaler with 4-Tap FilteringFiltering Line Buffers Formatter2.5 2-Tap Vertical and Horizontal Upscalers Ai,j Ai,j+1 Ai+1,jAi+1,j+1 Mixer/Blender Block RGBRAM YUV Valid Mixing/Blending Configurations YUV to RGB CSC in Video Data PathGamma Correction Color/Chroma Key Color/Chroma Key and Mixer/Blender Graphics WindowVideo Window Cursor Window Truth Table for Alpha Blending Mixing/Blending OperationColor CHROMASEL1 334 Vesa DDSC2B and Dpms Support Integrated DACsMonitor AMD Geode SC2200 Processor Data Book 335 Power Sequence TFT InterfaceHSYNC, VSYNC, TFTDE, Tftdck T1 is a programmable multiple of frame time T0+T1 Divider Phase Charge Loop Integrated PLLCompare Pump Filter Divider Out AMD Geode SC2200 Processor Data Book 337 F4BAR0 Video Processor Configuration Registers Summary Width Reset Reference F4 Index BitsF4 PCI Header Registers for Video Processor Support Summary F4BAR0+ Video Processor Module Register Summary AMD Geode SC2200 Processor Data Book 339 F4BAR2 VIP Support Registers Summary 32580BVideo Processor Module Register SummaryF4BAR2+ 340 Reset Value 0504h Reset Value 030000hVideo Processor Registers Function Video Processor Module Video Processor Registers Function Index 3Eh-FFh Reserved 342 F4 Index 10h, Base Address Register 0 F4BAR0 sets Base address that allows PCI access to the Video ProcesVideo Processor Support Registers F4BAR0 Offset 04h-07h Display Configuration Register R/W Tions of the power sequence control lines 16143028 Ddcsdaout DDC Output Data. DDC data bit for output Offset 08h-0Bh Video X Position Register R/W AMD Geode SC2200 Processor Data Book 345 Bit Description 100 346 Reset Value 00001400h 12 PLL2PWREN PLL2 Power-Down EnableBit Description Offset 1Ch-1Fh Block Offset 20h-23h DTS Downscale Type Select Offset 40h-43h Video Downscaler Coefficient Register R/WFLTCO4 Filter Coefficient 4. For the tap-4 filter FLTCO3 Filter Coefficient 3. For the tap-3 filter Reserved Signen Signature Enable Reset Value 0000xxxxhReset Value 00060000h Bit Description Offset 44h-47h CRC Signature Register R/W Top line is in even field. Default Top line is in odd field Cursor Color Key Register R/W Reset Value 00000000h100 i.e., shift one line otherwise, leave at 350 Incoming graphics stream to be ignored Offset 60h-63h Alpha Window 1 X Position Register R/W3125 Reserved AMD Geode SC2200 Processor Data Book 351 Reserved 352 3118Decremented until it is reloaded via bit 17 Loadalpha Reserved AMD Geode SC2200 Processor Data Book 353 Offset 90h-93h Offset 94h-97hOffset 400h-403h Video Fifo Underflow Empty Reserved. Set to Genlocktouten GenLock Timeout Enable Ctgenlocken Enable Continuous GenLock FunctionOffset 404h-407h Offset 408h-40Bh F4BAR0+Memory Offset Video Processor Configuration Registers F4BAR2+Memory Offset VIP Configuration Registers VIP Support Registers F4BAR2F4 Index 18h, Base Address Register 2 F4BAR2 points to AMD Geode SC2200 Processor Data Book 357 Capture Store to Memory VBI Data Capture Store to Memory Video DataReserved. Read Only Current Field. Read Only 2322 Bit Description Video Data Capture Active. Read Only Reserved. Read Only Run Status. Read Only3110 Reserved Start of each field Offset 14h-17h Offset 44h-47h VBI Data Even Base Register R/W Offset 48h-4Bh VBI Data Pitch Register R/W Jtag Mode Instruction Support Testability JtagMandatory Instruction Support Optional Instruction Support 366 General Specifications Power/Ground Connections and DecouplingElectro Static Discharge ESD Absolute Maximum Ratings Symbol Parameter Min Typ Max Unit Comments Operating ConditionsMultipliers 233 or 266 MHz 300 MHz Itor to VSS 233 or 266 MHz 300 MHz Power Planes of External Interface Signals Power Plane Signal Names VCC Balls VSS BallsPower State Parameter Definitions DC Current DC Characteristics for On State DC Characteristics for Active Idle, Sleep, and Off States Symbol ParameterNote Min Typ Max Unit Comments Symbol Parameter Min Typ Max Unit Comment Ball Capacitance and Inductance Pull-Up and Pull-Down Resistors Balls with PU/PD ResistorsVIO External PU or PD resistor DC Characteristics Symbol Description ReferenceWire 10. Buffer Types Inpci DC Characteristics Inab DC CharacteristicsInbtn DC Characteristics Instrp DC Characteristics INT DC CharacteristicsInts DC Characteristics INTS1 DC Characteristics Inusb DC Characteristics ODn DC Characteristics Odpci DC Characteristics N DC CharacteristicsOpci DC Characteristics Ousb DC Characteristics AC Characteristics 11. Default Levels for Measurement Switching ParametersSymbol Parameter Value CLK Inputs Memory Controller InterfaceOutputs 12. Memory Controller Timing Parameters SDCLK30, Sdclkout high time 233 MHz 266 MHz 300 MHz13.5 12.5 T1, t2, t3 SDCLK30 Control Output, MA120BA10, MD630 MD630 Data Valid Read Data Video Port 13. Video Input Port Timing Parameters Vpckin Vref CRT and TFT Interface 14. TFT Timing Parameters Symbol Parameter Note Min Max Unit Comments 15. CRT Vesa Compatible DAC RED, GREEN, and Blue Outputs 16. ACCESS.bus Input Timing Parameters 17. ACCESS.bus Output Timing Parameters AB1C AB2C AB1CAB1D AB2D 390 AB1D AB2D AB1C AB2CAB1D AB2D AB1C 18. PCI AC Specifications PCI Bus Interface Equation a Equation B 16VIO64VIO 19. PCI Clock Parameters Pciclk 0.4 V IO 20. PCI Timing Parameters Measurement and Test Conditions Symbol Value Unit Comments21. Measurement Condition Parameters Power SignalsInput Valid Ms typ Symbol Parameter Bits Type Comments Sub-ISA Interface22. Sub-ISA Timing Parameters Bus Width Min Bus Width Min Max Symbol Parameter Bits Type Comments DOCR#/IOR# ROMCS#/DOCCS# IOR#/RD#/TRDE#MEMR#/DOCR# IOW#/WR# MEMW#/DOCW# DOCCS#/ROMCS# IOCS10#IOW#/WR# MEMW#/DOCW# TRDE# D150 LPC Interface 23. LPC and Serirq Timing Parameters IDE signals fall time from 0.9V IO to 0.1V IO = 40 pF IDE signals rise time from 0.1V IO to 0.9V IO = 40 pFIDE Interface 24. IDE General Timing Parameters IDERST# pulse width Mode Symbol Parameter Unit Comments 25. IDE Register Transfer to/from Device Timing ParametersCycle time min Width 8-bit min Addr valid1 IDEIOR0# IDEIOW0# Write IDEDATA70Read IDEDATA70 IDEIORDY0 2,3 AMD Geode SC2200 Processor Data Book 405 26. IDE PIO Data Transfer to/from Device Timing Parameters165 125 100 406 IDEIOR0# IDEIOW0# Write IDEDATA150Read IDEDATA150 27. IDE Multiword DMA Data Transfer Timing Parameters 408 IDECS10#IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0# AMD Geode SC2200 Processor Data Book 409 Mode Symbol Parameter Min Max Unit Comments28. IDE UltraDMA Data Burst Timing Parameters IDEREQ0 STOP0IDEIOR0# HDMARDY0# IDEIRDY0 DSTROBE0 IDEIRDY0 DSTROBE0 at device IDEDATA150 at device IDEIRDY0 DSTROBE0 at hostIDEDATA150 at host AMD Geode SC2200 Processor Data Book 411 IDEDREQ0 device IDEDACK0# host IDEIOW0#STOP0 hostIDEIOR0#HDMARDY0# 412 AMD Geode SC2200 Processor Data Book 413 IDEDREQ0 deviceIDEIOW0# STOP0# IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# host IDEIRDY0 DSTROBE0 device IDEDATA150 deviceIDECS01# IDEADDR20 DevicetUI IDEDACK0# host IDEIOW0# STOP0# hostIDEIORDY0 DDMARDY0 device IDEIOR0# HSTROBE0# host HSTROBE0# At hostIDEDATA150 At host IDEIOR0# HSTROBE0# at device IDEDATA150 at device IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# host IDEIORDY0# DDMARDY0#IDEIOR0# HSTROBE0# AMD Geode SC2200 Processor Data Book 417 IDEIORDY0# DDMARDY0# device IDEDATA150 host IDEADDR20 IDECS01#IDEDACK0# host 418 AMD Geode SC2200 Processor Data Book 419 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# hostIDEDATA150 host IDECS01# IDEADDR20 Full Speed Receiver EOP Width Note Low Speed Source Note Source EOP width Host upstreamReceiver data jitter tolerance for paired Low Speed Receiver EOP Width Note Rise Time Fall Time Differential Data LinesDifferential Data Lines Crossover Points 2.0 Consecutive Transitions Differential Data to SE0 Skew Data Crossover LevelEOP Width Consecutive Transitio ns Modulation signal period TCPN + Transmitter Sharp-IR and Consumer Remote ControlSIR signal pulse width Setting of the Rxhsc bit bit 5 of the Rccfg register FIR Fast IR Port 31. Fast IR Port Timing ParametersMIR Busy ACK# STB# Unit Comments Symbol Parameter Min33. Enhanced Parallel Port Timing Parameters 34. ECP Forward Mode Timing Parameters Extended Capabilities Port ECPAFD# Busy 35. ECP Reverse Mode Timing Parameters BUSY# Audio Interface AC97 36. AC Reset Timing Parameters AC97RST# inactive to Bitclk 162.8 Startup delaySync inactive to Bitclk startup 162.8 Delay AC97RST# active low pulse width 38. AC97 Clocks Parameters AC97CLK Vold 39. AC97 I/O Timing Parameters SDATAOUT/SYNC SDATAIN, SDATAIN2 40. AC97 Signal Rise and Fall Timing Parameters 41. AC97 Low Power Mode Timing Parameters End of Slot 2 to Bitclk Sdatain lowSlot Bitclk Sdataout Power Management Power management event to ONCTL# Assertion42. PWRBTN# Timing Parameters ONCTL# PWRBTN# PWRBTN# ONTCL# PWRCNT21 POR# POR# 32KHZ AMD Geode SC2200 Processor Data Book 437 TDI, TMS setup time Non-test inputs setup timeJtag Interface 46. Jtag Timing Parameters TDI, TMS hold time Output Signals Input SignalsTDI TMS TDO AMD Geode SC2200 Processor Data Book 439 440 Case-to-Ambient Thermal Resistance Example @ 85C Thermal CharacteristicsΘJC ×C/W Heatsink Considerations ExampleAssume P max = 5W and TA max = 40C Therefore Assume P max = 9W and TA max = 40C Therefore AMD Geode SC2200 Processor Data Book 445 Physical DimensionsPackage Specifications BGU481 Package Bottom View 446 Order Information Ordering Part Number Core FrequencyMHz Degree C Package2 Revision # Revisions / Comments Data Book Revision HistoryTable A-1. Revision History