AMD Geode™ SC2200 Processor Data Book 383
Electrical Specifications 32580B
Table 9-12. Memory Controller Timing Parameters
Symbol Parameter Min Max Unit Comments
t1Control Output Valid from SDCLK[3:0] -3.0 + (x * y) 0.1 + (x * y) ns Note 1, Note 2
t2MA[12:0], BA[1.0] Output Valid from
SDCLK[3:0]
-3.2 + (x * y) 0.1 + (x * y) ns Note 2
t3MD[63:0] Output Valid from SDCLK[3:0] -2.2 + (x * y) 0.7 + (x * y) ns Note 2
t4MD[63:0] Read Data in Setup to
SDCLK_IN
1.3 ns
t5MD[63:0] Read Data Hold to SDCLK_IN 2.0 ns
t6SDCLK[3:0], SDCLK_OUT cycle time
233 MHz 10 14 ns
266 MHz 8.3 13.5
300 MHz 7.3 12.5
t7SDCLK[3:0], SDCLK_OUT fall/rise time
between (VOLD-VOHD)
2ns
t9SDCLK_IN fall/rise time between
(VILD-VIHD)
2ns
t10 SDCLK[3:0], SDCLK_OUT high time
233 MHz 4.0 ns
266 MHz 3.0
300 MHz 2.5
t11 SDCLK[3:0], SDCLK_OUT low time
233 MHz 4.0 ns
266 MHz 2.5
300 MHz 2.5
Note 1. Control output includes all the following signals: RASA#, CASA#, WEA#, CKEA, DQM[7:0], and CS[1:0]#.
Load = 50 pF, VCORE = 1.8V@ 233/266 MHz, VCORE = 2.1V@ 300 MHz, VIO = 3.3V, @25oC.
Note 2. Use the Min/Max equations [value+(x * y)] to calculate the actual output value.
x is the shift value which is applied to the SHFTSDCLK field, and y is 0.45 the core clock period.
Note that the SHFTSDCLK field = GX_BASE+Memory Offset 8404h[5:3]. Refer to the GX1 Processor Series Data
Book for more information.
For example, for a 266 MHz SC2200 running a 88.7 MHz SDRAM clock, with a shift value of 3:
t1 Min = -3 + (3 * (3.76 * 0.45)) = 2.08 ns
t1 Max = 0.1 + (3 * (3.76 * 0.45)) = 5.18 ns