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AMD SC2200 Table 9-25. IDE Register Transfer to/from Device Timing Parameters

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AMD Geode™ SC2200 Processor Data Book 403

Electrical Specifications 32580B

Table 9-25. IDE Register Transfer to/from Device Timing Parameters

Symbol Parameter

Mode

Unit Comments01235

t0Cycle time (min) 600 383 240 180 120 ns Note 1

t1Address valid to IDE_IOR[0:1]#/

IDE_IOW[0:1]# setup (min)

70 50 30 30 25 ns

t2IDE_IOR[0:1]#/IDE_IOW[0:1]# pulse

width 8-bit (min)

290 290 290 80 70 ns Note 1

t2i IDE_IOR[0:1]#/IDE_IOW[0:1]#

recovery time (min)

- - - 70 25 ns Note 1

t3IDE_IOW[0:1]# data setup (min) 6045303020ns

t4IDE_IOW[0:1]# data hold (min) 30 20 15 10 10 ns

t5IDE_IOR[0:1]# data setup (min) 5035202020ns

t6IDE_IOR[0:1]# data hold (min) 55555ns

t6Z IDE_IOR[0:1]# data TRI-STATE

(max)

30 30 30 30 30 ns Note 2

t9IDE_IOR[0:1]#/IDE_IOW[0:1]# to

address valid hold (min)

20 15 10 10 10 ns

tRD Read data valid to IDE_IORDY[0:1]

active (if IDE_IORDY[0:1] initially low

after tA (min)

00000ns

tAIDE_IORDY[0:1] setup time 35 35 35 35 35 ns Note 3

tBIDE_IORDY[0:1] pulse width (max) 1250 1250 1250 1250 1250 ns

tCIDE_IORDY[0:1] assertion to release

(max)

55555ns

Note 1. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recov-

ery time or command inactive time. The actual cycle time equals the sum of the command active time and the com-

mand inactive time. The three timing requirements of t0, t2, and t2i are met. The minimum total cycle time

requirements is greater than the sum of t2 and t2i. (This means that a host implementation can lengthen t2 and/or

t2i to ensure that t0 is equal to or greater than the value reported in the device’s IDENTIFY DEVICE data.)

Note 2. This parameter specifies the time from the rising edge of IDE_IOR[0:1]# to the time that the data bus is no longer

driven by the device (TRI-STATE).

Note 3. The delay from the activation of IDE_IOR[0:1]# or IDE_IOW[0:1]# until the state of IDE_IORDY[0,1] is first sampled.

If IDE_IORDY[0:1] is inactive, then the host waits until IDE_IORDY[0:1] is active before the PIO cycle is completed.

If the device is not driving IDE_IORDY[0:1] negated after activation (tA) of IDE_IOR[0:1]# or IDE_IOW[0:1]#, then

t5 is met and tRD is not applicable. If the device is driving IDE_IORDY[0:1] negated after activation (tA) of

IDE_IOR[0:1]# or IDE_IOW[0:1]#, then tRD is met and t5 is not applicable.

Contents

Main Page Contents Page List of Figures Page Page Page List of Tables Page Page Page 1.0Overview 1.1 General Description Figure 1-1. Block Diagram GX1 Video Processor 1.2 Features General Features Page Page 2.0Architecture Overview 2.1 GX1 Module 2.1.1 Memory Controller Table 2-1. SC2200 Memory Controller Register Summary Table 2-2. SC2200 Memory Controller Registers Page Page Table 2-2. SC2200 Memory Controller Registers (Continued) 2.1.2 Fast-PCI Bus 2.1.3 Display 2.2 Video Processor Module 2.2.1 GX1 Module Interface 2.2.2 Video Input Port 2.2.3 Core Logic Module Interface 2.2.4 CRT DAC 2.3 Core Logic Module 2.3.1 Other Interfaces of the Core Logic Module 2.4 SuperI/O Module 2.5 Clock, Timers, and Reset Logic 2.5.1 Reset Logic AMD Geode SC2200 Processor Data Book 25 Signal Definitions 32580B appropriate functional group. 3.0Signal Definitions TFT Interface Parallel Port/ CRT System Figure 3-1. Signal Groups (Continued) Serial Ports GPIO/LPC Bus JTAG Power 3.1 Ball Assignments Table 3-1. Signal Definitions Legend (Top View) Figure 3-2. BGU481 Ball Assignment Diagram Note: Signal names have been abbreviated in this figure due to space constraints. AMD Geode SC2200 Processor Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number Page Page 32 AMD Geode SC2200 Processor Data Book 32580B Page Page Page Page Page Page Table 3-3. BGU481 Ball Assignment - Sorted Alphabetically by Signal Name Page Page Page 3.2 Strap Options Table 3-4. Strap Options 3.3 Multiplexing Configuration Table 3-5. Two-Signal/Group Multiplexing Table 3-5. Two-Signal/Group Multiplexing (Continued) Table 3-6. Three-Signal/Group Multiplexing Table 3-6. Three-Signal/Group Multiplexing (Continued) Table 3-7. Four-Signal/Group Multiplexing 3.4 Signal Descriptions 3.4.1 System Interface 3.4.1 System Interface (Continued) 3.4.2 Memory Interface Signals 3.4.2 Memory Interface Signals (Continued) 3.4.3 Video Port Interface Signals 3.4.4 CRT/TFT Interface Signals 3.4.5 ACCESS.bus Interface Signals 3.4.5 ACCESS.bus Interface Signals (Continued) 3.4.6 PCI Bus Interface Signals Page Page Page 3.4.7 Sub-ISA Interface Signals 3.4.8 Low Pin Count (LPC) Bus Interface Signals 3.4.9 IDE Interface Signals 3.4.10 Universal Serial Bus (USB) Interface Signals 3.4.11 Serial Ports (UARTs) Interface Signals 3.4.11 Serial Ports (UARTs) Interface Signals (Continued) 3.4.12 Parallel Port Interface Signals 3.4.12 Parallel Port Interface Signals (Continued) 3.4.13 Fast Infrared (IR) Port Interface Signals 3.4.14 AC97 Audio Interface Signals 3.4.15 Power Management Interface Signals 3.4.15 Power Management Interface Signals (Continued) 3.4.16 GPIO Interface Signals 3.4.17 Debug Monitoring Interface Signals 3.4.18 JTAG Interface Signals 3.4.18 JTAG Interface Signals (Continued) 3.4.19 Test and Measurement Interface Signals 3.4.20 Power, Ground and No Connections1 3.4.20 Power, Ground and No Connections1 (Continued) Page 4.0General Configuration Block 4.1 Configuration Block Addresses Table 4-1. General Configuration Block Register Summary 4.2 Multiplexing, Interrupt Selection, and Base Address Registers Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers Page Page Page Page Page Page 4.3 WATCHDOG 4.3.1 Functional Description Figure 4-1. WATCHDOG Block Diagram WATCHDOG 4.3.2 WATCHDOG Registers Table 4-3. WATCHDOG Registers 4.4 High-Resolution Timer 4.4.1 Functional Description 4.4.2 High-Resolution Timer Registers Table 4-3. WATCHDOG Registers (Continued) Table 4-4. High-Resolution Timer Registers 4.5 Clock Generators and PLLs Note: VPLL2 powers PLL2 and PLL5. VPLL3 powers PLL3, PLL4, and PLL6. Figure 4-2. Clock Generation Block Diagram 4.5.1 27 MHz Crystal Oscillator Figure 4-3. Recommended Oscillator External Circuitry Table 4-5. Crystal Oscillator Circuit Components 4.5.2 GX1 Module Core Clock 4.5.3 Internal Fast-PCI Clock Table 4-6. Core Clock Frequency Table 4-7. Strapped Core Clock Frequency 4.5.4 SuperI/O Clocks 4.5.5 Core Logic Module Clocks 4.5.6 Video Processor Clocks 4.5.7 Clock Registers Table 4-9 describes the registers of the clock generator and PLL. Table 4-8. Clock Generator Configuration Table 4-8. Clock Generator Configuration (Continued) 5.0SuperI/O Module Figure 5-1. SIO Block Diagram 5.1 Features 5.2 Module Architecture Figure 5-2. Detailed SIO Block Diagram 5.3 Configuration Structure/Access 5.3.1 Index-Data Register Pair 5.3.2 Banked Logical Device Registers Figure 5-3. Structure of the Standard Configuration Register File Table 5-1. SIO Configuration Options 5.3.3 Default Configuration Setup 5.3.4 Address Decoding 5.4 Standard Configuration Registers Figure 5-4. Standard Configuration Registers Map Page Table 5-3. Standard Configuration Registers 5.4.1 SIO Control and Configuration Registers Table 5-4. SIO Control and Configuration Register Map Table 5-5. SIO Control and Configuration Registers 5.4.2 Logical Device Control and Configuration Table 5-6. Relevant RTC Configuration Registers Table 5-7. RTC Configuration Registers Table 5-8. Relevant SWC Registers Table 5-9. Relevant IRCP/SP3 Registers Table 5-10. IRCP/SP3 Configuration Register Table 5-11. Relevant Serial Ports 1 and 2 Registers Table 5-12. Serial Ports 1 and 2 Configuration Registe r Table 5-13. Relevant ACB1 and ACB2 Registers Table 5-14. ACB1 and ACB2 Configuration Register Table 5-15. Relevant Parallel Port Registers Table 5-16. Parallel Port Configuration Register 5.5 Real-Time Clock (RTC) 5.5.1 Bus Interface 5.5.2 RTC Clock Generation Figure 5-5. Recommended Oscillator External Circuitry Table 5-17. Crystal Oscillator Circuit Components Figure 5-6. External Oscillator Connections Figure 5-7. Divider Chain Control Page Figure 5-8. Power Supply Connections Figure 5-9. Typical Battery Configuration Figure 5-10. Typical Battery Current: Battery Backed Power Mode @ TC = 25C Figure 5-11. Typical Battery Current: Normal Operation Mode Table 5-18. System Power States Figure 5-12. Interrupt/Status Timing 5.5.3 RTC Registers Table 5-19. RTC Register Map Table 5-20. RTC Registers Page Table 5-20. RTC Registers (Continued) Table 5-21. Divider Chain Control / Test Selection Table 5-22. Periodic Interrupt Rate Encoding Table 5-23. BCD and Binary Formats 5.5.4 RTC General-Purpose RAM Map Table 5-24. Standard RAM Map Table 5-25. Extended RAM Map 5.6 System Wakeup Control (SWC) 5.6.1 Event Detection Table 5-26. Time Range Limits for CEIR Protocols 5.6.2 SWC Registers Table 5-27. Banks 0 and 1 - Common Control and Status Register Map Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map Table 5-29. Banks 0 and 1 - Common Control and Status Registers Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers (Continued) 5.7 ACCESS.bus Interface 5.7.1 Data Transactions Figure 5-14. Start and Stop Conditions Figure 5-13. Bit Transfer 5.7.2 Start and Stop Conditions 5.7.3 Acknowledge (ACK) Cycle Figure 5-15. ACCESS.bus Data Transaction Figure 5-16. ACCESS.bus Acknowledge Cycle 5.7.4 Acknowledge After Every Byte Rule 5.7.5 Addressing Transfer Formats 5.7.6 Arbitration on the Bus 5.7.7 Master Mode Figure 5-17. A Complete ACCESS.bus Data Transaction Page 5.7.8 Slave Mode or 5.7.9 Configuration 5.7.10 ACB Registers Table 5-31. ACB Register Map Table 5-32. ACB Registers Page Table 5-32. ACB Registers (Continued) 5.8 Legacy Functional Blocks 5.8.1 Parallel Port Table 5-33. Parallel Port Register Map for First Level Offset Table 5-34. Parallel Port Register Map for Second Level Offset Table 5-35. Parallel Port Bit Map for First Level Offset Table 5-36. Parallel Port Bit Map for Second Level Offset 5.8.2 UART Functionality (SP1 and SP2) Figure 5-18. UART Mode Register Bank Architecture Table 5-37. Bank 0 Register Map Table 5-38. Bank Selection Encoding Table 5-39. Bank 1 Register Map Table 5-40. Bank 2 Register Map Table 5-41. Bank 3 Register Map Table 5-42. Bank 0 Bit Map Table 5-43. Bank 1 Bit Map Table 5-44. Bank 2 Bit Map Table 5-45. Bank 3 Bit Map 5.8.3 IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality Figure 5-19. IRCP/SP3 Register Bank Architecture Table 5-46. Bank 0 Register Map Table 5-47. Bank Selection Encoding Table 5-48. Bank 1 Register Map Table 5-49. Bank 2 Register Map Table 5-50. Bank 3 Register Map Table 5-51. Bank 4 Register Map Table 5-52. Bank 5 Register Map Table 5-53. Bank 6 Register Map Table 5-54. Bank 7 Register Map Table 5-55. Bank 0 Bit Map Table 5-56. Bank 1 Bit Map Table 5-57. Bank 2 Bit Map Table 5-58. Bank 3 Bit Map Table 5-59. Bank 4 Bit Map Table 5-59. Bank 4 Bit Map (Continued) Table 5-60. Bank 5 Bit Map Table 5-61. Bank 6 Bit Map Table 5-62. Bank 7 Bit Map 6.0Core Logic Module 6.1 Feature List 6.2 Module Architecture Figure 6-1. Core Logic Module Block Diagram 6.2.1 Fast-PCI Interface to External PCI Bus 6.2.2 PSERIAL Interface 6.2.3 IDE Controller Table 6-1. Physical Region Descriptor Format Table 6-2. UltraDMA/33 Signal Definitions 6.2.4 Universal Serial Bus 6.2.5 Sub-ISA Bus Interface Figure 6-2. Non-Posted Fast-PCI to ISA Access Figure 6-3. PCI to ISA Cycles with Delayed Transaction Enabled Figure 6-4. ISA DMA Read from PCI Memory Figure 6-5. ISA DMA Write to PCI Memory Table 6-3. Cycle Multiplexed PCI / Sub-ISA Balls Figure 6-6. PCI Change to Sub-ISA and Back 6.2.6 AT Compatibility Logic Page Figure 6-7. PIT Timer Figure 6-8. PIC Interrupt Controllers Table 6-4. PIC Interrupt Mapping Figure 6-9. PCI and IRQ Interrupt Mapping 6.2.7 I/O Ports 092h and 061h System Control 6.2.8 Keyboard Support Figure 6-10. SMI Generation for NMI 6.2.9 Power Management Logic Table 6-5. Wakeup Events Capability Table 6-6. Power Planes Control Signals vs. Sleep States Table 6-7. Power Planes vs. Sleep/Global States Table 6-8. Power Management Events Page 6.2.10 Power Management Programming Page Page Figure 6-11. General Purpose Timer and UDEF Trap SMI Tree Example Table 6-9. Device Power Management Programming Summary 6.2.11 GPIO Interface 6.2.12 Integrated Audio Table 6-10. Bus Masters That Drive Specific Slots of the AC97 Interface Table 6-11. Physical Region Descriptor Format Figure 6-12. PRD Table Example Figure 6-13. AC97 V2.0 Codec Signal Connections AMD Geode SC2200 Processor Page Figure 6-14. Audio SMI Tree Example GX1 Core Logic Module Module Figure 6-15. Typical Setup Table 6-12. Cycle Types 6.3 Register Descriptions 6.3.1 PCI Configuration Space and Access Methods Table 6-13. PCI Configuration Address Register (0CF8h) 6.3.2 Register Summary Table 6-14. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support Summary Page Page Table 6-15. F0BAR0: GPIO Support Registers Summary Table 6-16. F0BAR1: LPC Support Registers Summary Table 6-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary Table 6-18. F1BAR0: SMI Status Registers Summary Table 6-19. F1BAR1: ACPI Support Registers Summary Table 6-20. F2: PCI Header Registers for IDE Controller Support Summary Table 6-21. F2BAR4: IDE Controller Support Registers Summary Table 6-22. F3: PCI Header Registers for Audio Support Summary Table 6-23. F3BAR0: Audio Support Registers Summary Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary Table 6-25. F5BAR0: I/O Control Support Registers Summary Table 6-26. PCIUSB: USB PCI Configuration Register Summary Table 6-27. USB_BAR: USB Controller Registers Summary Table 6-28. ISA Legacy I/O Register Summary Table 6-28. ISA Legacy I/O Register Summary (Continued) 6.4 Chipset Register Space 6.4.1 Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Suppo rt Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers Page Page Page Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers Page Page Page Page Page Page Page 6.4.2 SMI Status and ACPI Registers - Function 1 Table 6-32. F1: PCI Header Registers for SMI Status and ACPI Support Table 6-33. F1BAR0+I/O Offset: SMI Status Registers Page Page Page Page Page Page Page Page are located. Table 6-34 shows the I/O mapped ACPI Sup- port registers accessed through F1BAR1. Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers Page Page Page Page Page Page Page Page 6.4.3 IDE Controller Registers - Function 2 Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration Page Page Page mats of the I/O mapped IDE Controller Configuration registers that are accessed through F2BAR4. Table 6-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers Table 6-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers (Continued) 6.4.4 Audio Registers - Function 3 Table 6-37. F3: PCI Header Registers for Audio Configuration memory mapped audio configuration registers that are accessed through F3BAR0. Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers Page Page Page Page Page Page Page Page Page Page Page Page Page 6.4.5 X-Bus Expansion Interface - Function 5 Table 6-39. F5: PCI Header Registers for X-Bus Expansion Page Page trol support registers. Table 6-40 shows the support regis- ters accessed through F5BAR0. Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Registers Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Regist ers (Continued) 6.4.6 USB Controller Registers - PCIUSB Table 6-41. PCIUSB: USB PCI Configuration Registers Page Table 6-41. PCIUSB: USB PCI Configuration Registers (Continued) Table 6-42. USB_BAR+Memory Offset: USB Controller Registers Page Page Page Page Page Page Page Page Page 6.4.7 ISA Legacy Register Space Table 6-43. DMA Channel Control Registers Page Page Page Page Table 6-44. DMA Page Registers Table 6-45. Programmable Interval Timer Registers Table 6-45. Programmable Interval Timer Registers (Continued) Table 6-46. Programmable Interrupt Controller Registers Page Table 6-46. Programmable Interrupt Controller Registers (Continued) Table 6-47. Keyboard Controller Registers Table 6-48. Real-Time Clock Registers Table 6-49. Miscellaneous Registers Table 6-49. Miscellaneous Registers (Continued) 7.0Video Processor Module 7.1 Module Architecture Figure 7-1. Video Processor Block Diagram 7.2 Functional Description Figure 7-2. NTSC 525 Lines, 60 Hz, Odd Field Figure 7-3. NTSC 525 Lines, 60 Hz, Even Field Active Video 7.2.1 Video Input Port (VIP) VIP Figure 7-4. VIP Block Diagram Page Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers 7.2.2 Video Block Figure 7-7. Video Block Diagram Figure 7-8. Horizontal Downscaler Block Diagram Page 7.2.3 Mixer/Blender Block Figure 7-10. Mixer/Blender Block Diagram Table 7-1. Valid Mixing/Blending Configurations Figure 7-11. Graphics/Video Frame with Alpha Windows Table 7-2. Truth Table for Alpha Blending Figure 7-12. Color Key and Alpha Blending Logic 7.2.4 VESA DDSC2B and DPMS Support 7.2.5 Integrated DACs Figure 7-13. DAC Voltage Levels 7.2.6 TFT Interface Figure 7-14. TFT Power Sequence 7.2.7 Integrated PLL Figure 7-15. PLL Block Diagram 7.3 Register Descriptions 7.3.1 Register Summary Table 7-3. F4: PCI Header Registers for Video Processor Support Summary Table 7-4. F4BAR0: Video Processor Configuration Registers Summary Table 7-4. F4BAR0: Video Processor Configuration Registers Summary (Continued) Table 7-5. F4BAR2: VIP Support Registers Summary 7.3.2 Video Processor Registers - Function 4 Table 7-6. F4: PCI Header Registers for Video Processor Support Registers Page Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers Page Page Page Page Page Page Page Page Page Page Page Page Page are located. Table 7-8 shows the memory mapped VIP sup- port registers accessed through F4BAR2. Table 7-8. F4BAR2+Memory Offset: VIP Configuration Registers Page Page Page 8.0Debugging and Monitoring 8.1 Testability (JTAG) 8.1.1 Mandatory Instruction Support 8.1.2 Optional Instruction Support 8.1.3 JTAG Chain Page 9.0Electrical Specifications 9.1 General Specifications 9.1.1 Electro Static Discharge (ESD) 9.1.2 Power/Ground Connections and Decoupling 9.1.3 Absolute Maximum Ratings 9.1.4 Operating Conditions Table 9-3. Operating Conditions 9.1.5 DC Current Table 9-4. Power Planes of External Interface Signals Table 9-5. System Conditions Used to Measure SC2200 Current During the On State Table 9-6. DC Characteristics for On State Table 9-6. DC Characteristics for On State (Continued) Table 9-7. DC Characteristics for Active Idle, Sleep, and Off States 9.1.6 Ball Capacitance and Inductance Table 9-8. Ball Capacitance and Inductance 9.1.7 Pull-Up and Pull-Down Resistors Table 9-9. Balls with PU/PD Resistors 9.2 DC Characteristics Table 9-10. Buffer Types 9.2.1 INAB DC Characteristics 9.2.2 INBTN DC Characteristics 9.2.3 INPCI DC Characteristics 9.2.4 INSTRP DC Characteristics 9.2.5 INT DC Characteristics 9.2.7 INTS1 DC Characteristics 9.2.6 INTS DC Characteristics 9.2.8 INUSB DC Characteristics Figure 9-1. Differential Input Sensitivity for Common Mode Range 9.2.9 OAC97 DC Characteristics 9.2.10 ODn DC Characteristics 9.2.11 ODPCI DC Characteristics 9.2.12 Op/n DC Characteristics 9.2.13 OPCI DC Characteristics 9.2.14 OUSB DC Characteristics 9.2.15 TSp/n DC Characteristics 9.3 AC Characteristics Figure 9-2. General Drive level and Measurement Points Table 9-11. Default Levels for Measurement of Switching Parameters 9.3.1 Memory Controller Interface Figure 9-3. Drive Level and Measurement Points Table 9-12. Memory Controller Timing Parameters Figure 9-4. Memory Controller Output Valid Timing Diagram Figure 9-5. Read Data In Setup and Hold Timing Diagram 9.3.2 Video Port Figure 9-6. Video Input Port Timing Diagram Table 9-13. Video Input Port Timing Parameters t PCK_FR t t t V 9.3.3 CRT and TFT Interface Figure 9-7. TFT Timing Diagram Table 9-14. TFT Timing Parameters Table 9-15. CRT VESA Compatible DAC (RED, GREEN, and BLUE Outputs) 9.3.4 ACCESS.bus Interface Table 9-16. ACCESS.bus Input Timing Parameters Table 9-17. ACCESS.bus Output Timing Parameters Figure 9-8. ACB Signals: Rising Time and Falling Timing Diagram Figure 9-9. ACB Start and Stop Condition Timing Diagram Table 9-17. ACCESS.bus Output Timing Parameters (Continued) Figure 9-10. ACB Start Condition Timing Diagram Figure 9-11. ACB Data Bit Timing Diagram 9.3.5 PCI Bus Interface Figure 9-12. Testing Setup for Slew Rate and Minimum Timing Table 9-18. PCI AC Specifications Figure 9-13. V/I Curves for PCI Output Signals Figure 9-14. PCICLK Timing and Measurement Points Table 9-19. PCI Clock Parameters Figure 9-15. Load Circuits for Maximum Time Measurements Table 9-20. PCI Timing Parameters Figure 9-16. Output Timing Measurement Conditions Table 9-21. Measurement Condition Parameters Figure 9-17. Input Timing Measurement Conditions Figure 9-18. PCI Reset Timing 9.3.6 Sub-ISA Interface Table 9-22. Sub-ISA Timing Parameters Table 9-22. Sub-ISA Timing Parameters (Continued) Figure 9-19. Sub-ISA Read Operation Timing Diagram Figure 9-20. Sub -ISA Write Operation Timing Diagram 9.3.7 LPC Interface Figure 9-21. LPC Output Timing Diagram Figure 9-22. LPC Input Timing Diagram Table 9-23. LPC and SERIRQ Timing Parameters 9.3.8 IDE Interface Figure 9-23. IDE Reset Timing Diagram Table 9-24. IDE General Timing Parameters Table 9-25. IDE Register Transfer to/from Device Timing Parameters Figure 9-24. Register Transfer to/from Device Timing Diagram Table 9-26. IDE PIO Data Transfer to/from Device Timing Parameters Figure 9-25. PIO Data Transfer to/from Device Timing Diagram Table 9-27. IDE Multiword DMA Data Transfer Timing Parameters Figure 9-26. Multiword DMA Data Transfer Timing Diagram Table 9-28. IDE UltraDMA Data Burst Timing Parameters Figure 9-27. Initiating an UltraDMA Data in Burst Timing Diagram Figure 9-28. Sustained UltraDMA Data In Burst Timing Diagram Figure 9-29. Host Pausing an UltraDMA Data In Burst Timing Diagram Figure 9-30. Device Terminating an UltraDMA Data In Burst Timing Diagram Figure 9-31. Host Terminating an UltraDMA Data In Burst Timing Diagram Figure 9-32. Initiating an UltraDMA Data Out Burst Timing Diagram Figure 9-33. Sustained UltraDMA Data Out Burst Timing Diagram Figure 9-34. Device Pausing an UltraDMA Data Out Burst Timing Diagram Figure 9-35. Host Terminating an UltraDMA Data Out Burst Timing Diagram Figure 9-36. Device Terminating an UltraDMA Data Out Burst Timing Diagram 9.3.9 Universal Serial Bus (USB) Interface Table 9-29. USB Timing Parameters Table 9-29. USB Timing Parameters (Continued) Figure 9-37. Data Signal Rise and Fall Timing Diagram Figure 9-38. Source Differential Data Jitter Timing Diagram N*t _ + t Figure 9-39. EOP Width Timing Diagram Figure 9-40. Receiver Jitter Tolerance Timing Diagram 9.3.10 Serial Port (UART) Figure 9-41. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram Table 9-30. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Parameters t 9.3.11 Fast IR Port Figure 9-42. Fast IR (MIR and FIR) Timing Diagram Table 9-31. Fast IR Port Timing Parameters 9.3.12 Parallel Port Interface Figure 9-43. Standard Parallel Port Typical Data Exchange Timing Diagram Table 9-32. Standard Parallel Port Timing Parameters Figure 9-44. Enhanced Parallel Port Timing Diagram Table 9-33. Enhanced Parallel Port Timing Parameters Figure 9-45. ECP Forward Mode Timing Diagram Table 9-34. ECP Forward Mode Timing Parameters Figure 9-46. ECP Reverse Mode Timing Diagram Table 9-35. ECP Reverse Mode Timing Parameters 9.3.13 Audio Interface (AC97) Figure 9-47. AC97 Reset Timing Diagram Figure 9-48. AC97 Sync Timing Diagram Table 9-36. AC Reset Timing Parameters Table 9-37. AC97 Sync Timing Parameters Figure 9-49. AC97 Clocks Diagram Table 9-38. AC97 Clocks Parameters Figure 9-50. AC97 Data TIming Diagram Table 9-39. AC97 I/O Timing Parameters t t Figure 9-51. AC97 Rise and Fall Timing Diagram Table 9-40. AC97 Signal Rise and Fall Timing Parameters Figure 9-52. AC97 Low Power Mode Timing Diagram Table 9-41. AC97 Low Power Mode Timing Parameters 9.3.14 Power Management Figure 9-53. PWRBTN# Trigger and ONCTL# Timing Diagram Figure 9-54. GPWIO a nd ONCTL# Timing Diagram Table 9-42. PWRBTN# Timing Parameters Table 9-43. Power Management Event (GPWIO) and ONCTL# Tim ing Parameters 9.3.15 Power-Up Sequencing Figure 9-55. Power-Up Sequencing With PWRBTN# Timing Diagram Table 9-44. Power-Up Sequence Using the Power Button Timing Parameters Figure 9-56. Power-Up Sequencing Without PWRBTN# Timing Diagram Table 9-45. Power-Up Sequence Not Using the Power Button Timing Parameters 9.3.16 JTAG Interface Figure 9-57. TCK Measurement Points and Timing Diagram Table 9-46. JTAG Timing Parameters Figure 9-58. JTAG Test Timing Diagram Page 10.0Package Specifications 10.1 Thermal Characteristics Table 10-1. JC (C/W) Table 10-2. Case-to-Ambient Thermal Resistance Example @ 85C 10.1.1 Heatsink Considerations Page Page Appendix ASupport Documentation A.1 Order Information A.2 Data Book Revision History Table A-1. Revision History