AMD SC2200 Those selected GPIOs for generation of an SCI, Offset 15h Gpwio Control Register 2 R/W

Core Logic Module - SMI Status and ACPI Registers - Function 1 32580B

Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)

Bit Description

3GPIO_EN. Allow GPIOs (GPIO47-GPIO32 and GPIO15-GPIO0) to generate an SCI.

0:Disable.

1:Enable.

	F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled for PME generation. This bit (GPIO_EN) globally enables
	those selected GPIOs for generation of an SCI.
2:1	Reserved. Must be set to 0.

0PWR_U_REQ_EN. Allow power-up request events from the SuperI/O module to generate an SCI.

0:Disable.

1:Enable.

A power-up request event is defined as any of the following events/activities: Modem, Telephone, Keyboard, Mouse, CEIR (Consumer Electronic Infrared)

Offset	14h	GPWIO Control Register 1 (R/W)	Reset Value: 00h
7:4		Reserved. Must be set to 0.

3Reserved.

2GPWIO2_POL. Select GPWIO2 polarity.

0:Active high.

1:Active low.

1GPWIO1_POL. Select GPWIO1 polarity.

0:Active high.

1:Active low.

0GPWIO0_POL. Select GPWIO0 polarity.

0:Active high.

1:Active low.

Offset 15h GPWIO Control Register 2 (R/W) Reset Value: 00h

7Reserved.

6GPWIO_SMIEN2. Allow GPWIO2 to generate an SMI.

0:Disable. (Default)

1:Enable.

A fixed high-to-low or low-to-high transition (debounce period) of 31 µs exists in order for GPWIO2 to be recognized. Bit 2 of this register must be set to 0 (input) for GPWIO2 to be able to generate an SMI.

If asserted, this bit overrides the setting of F1BAR1+I/O Offset 12h[10] and its status is reported in F1BAR0+I/O Offset 00h/ 02h[0].

5GPWIO_SMIEN1. Allow GPWIO1 to generate an SMI.

0:Disable. (Default)

1:Enable.

See F1BAR1+I/O Offset 07h[3] for debounce information.

Bit 1 of this register must be set to 0 (input) for GPWIO1 to be able to generate an SMI.

If asserted, this bit overrides the setting of F1BAR1+I/O Offset 12h[9] and its status is reported in F1BAR0+I/O Offset 00h/ 02h[0].

4GPWIO_SMIEN0. Allow GPWIO0 to generate an SMI.

0:Disable. (Default)

1:Enable.

See F1BAR1+I/O Offset 07h[3] for debounce information.

Bit 0 of this register must be set to 0 (input) for GPWIO0 to be able to generate an SMI.

If enabled, this bit overrides the setting of F1BAR1+I/O Offset 12h[8] and its status is reported in F1BAR0+I/O Offset 00h/ 02h[0].

3Reserved.

AMD Geode™ SC2200 Processor Data Book 261