Signal Definitions

32580B

3.4.1System Interface (Continued)

Signal Name

Ball No.

Type

Description

Mux

 

 

 

 

 

X32I

AJ2

I/O

Crystal Connections. Connected directly to a 32.768

---

 

 

 

KHz crystal. This clock input is required even if the inter-

 

X32O

AJ3

 

---

 

nal RTC is not being used. Some of the internal clocks

 

 

 

 

 

 

 

are derived from this clock. If an external clock is used, it

 

 

 

 

should be connected to X32I, using a voltage level of 0

 

 

 

 

volts to VCORE +10% maximum. X32O should remain

 

 

 

 

unconnected.

 

 

 

 

 

 

X27I

AG3

I/O

Crystal Connections. Connected directly to a

---

 

 

 

27.000 MHz crystal. Some of the internal clocks are

 

X27O

AH2

 

---

 

derived from this clock. If an external clock is used, it

 

 

 

 

 

 

 

should be connected to X27I, using a voltage level of 0

 

 

 

 

volts to VIO and X27O should be remain unconnected.

 

CLK27M

AA4

O

27 MHz Output Clock. Output of crystal oscillator.

IDE_DATA5

 

 

 

 

 

PCIRST#

A6

O

PCI and System Reset. PCIRST# is the reset signal for

---

 

 

 

the PCI bus and system. It is asserted for approximately

 

 

 

 

100 µs after POR# is negated.

 

 

 

 

 

 

AMD Geode™ SC2200 Processor Data Book

53

Page 49
Image 49
AMD SC2200 manual AJ2, AJ3, AG3, AH2, CLK27M AA4, Pcirst#