AMD SC2200 3.4.2 Memory Interface Signals (Continued), 3.4.3 Video Port Interface Signals

AMD Geode™ SC2200 Processor Data Book 55
Signal Definitions 32580B
SDCLK_IN AJ27 I SDRAM Clock Input. The SC2200 samples the memory
read data on this clock. Works in conjunction with the
SDCLK_OUT signal.
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SDCLK_OUT AK28 O SDRAM Clock Output. This output is routed back to
SDCLK_IN. The board designer should vary the length of
the board trace to control skew between SDCLK_IN and
SDCLK.
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3.4.2 Memory Interface Signals (Continued)
Signal Name Ball No. Type Description Mux
3.4.3 Video Port Interface Signals
Signal Name Ball No. Type Description Mux
VPD7 G31 I Video Port Data. The data is input from the CCIR-656
video decoder.
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VPD6 H28 ---
VPD5 H29 ---
VPD4 H30 ---
VPD3 H31 ---
VPD2 J28 ---
VPD1 J29 ---
VPD0 J30 ---
VPCKIN F31 I Video Port Clock Input. The clock input from the video
decoder.
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