Electrical Specifications

32580B

9.3.7LPC Interface

Table 9-23. LPC and SERIRQ Timing Parameters

Symbol

Parameter

Min

Max

Unit

Comments

 

 

 

 

 

 

tVAL

Output Valid delay

0

17

ns

After PCICLK rising edge

tON

Float to Active delay

2

 

ns

After PCICLK rising edge

tOFF

Active to Float delay

 

28

ns

After PCICLK rising edge

tSU

Input Setup time

7

 

ns

Before PCICLK rising edge

tHI

Input Hold time

0

 

ns

After PCICLK rising edge

PCICLK

tVAL

tON

LPC Signals/

SERIRQ

tOFF

Figure 9-21. LPC Output Timing Diagram

PCICLK

 

 

 

 

tSU

tHI

LPC Signals/

 

 

 

 

 

 

 

 

Input

 

SERIRQ

 

Valid

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 9-22. LPC Input Timing Diagram

AMD Geode™ SC2200 Processor Data Book

401

Page 383
Image 383
AMD SC2200 manual LPC Interface 23. LPC and Serirq Timing Parameters