FPGA | Devices’ Features and Data Paths |
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During a hard reset all internal registers, state machines and caches of the CPU are reset. Furthermore all on−board PCI devices as well as the host bridge are reset.a
During a soft reset the CPU is reset, with the exception of the internal caches and state machinesaaa
Reset Sources
The following table lists all possible reset sources and the corresponding reset types.aaa
Table 10: Reset Sources
Reset Source | Hard Reset | Soft Reset |
Software reset | x | x |
Watchdog inside Southbridge | x |
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Power−up reset | x |
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Face plate reset key | x |
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RTM reset | x |
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IPMC reset | x |
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Keyboard reset |
| x |
Interrupt Routing Unit
The FPGA is used for fixed interrupt routing on the blade.a
All interrupts from PCI devices are routed via the FPGA to the South Bridge. All other interrupts are routed to the Super I/O device from where they are routed to the South Bridge.a
Miscellaneous Glue Logic
The miscellaneous glue logic includes:
SSerial interface
SReset mask and source register
SFlash control register
SPMC status register
SShut−down register
PENT/ATCA−717 | 117 |
