FPGA Registers | Maps and Registers |
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DPLL Input Select and Control Register
Table 29: DPLL Input Select and Control Register
Bit | Description | Default | Access |
0 | Selects DPLL clock sourcea | 02 | r/w |
| 0: System clock |
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| 1: Reference clock |
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1 | Selects system clock source CLK1 or CLK2 | 02 | r/w |
| 0: CLK2 |
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| 1: CLK1 |
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2 | Unused | 02 | r |
3 | SPI interface is ready for access | 12 | r |
| 0: Wait |
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| 1: SPI Ready |
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4 | Enabling of 2 kHz system clock interrupt | 02 | r/w |
| 0: Disabled |
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| 1: Enabled |
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5 | 2 kHz system clock interrupt status | 02 | r |
| 0: Not active |
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| 1: Interrupt pending |
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6 | Clear 2 kHz system clock interrupt | − | r/w |
| Writing 0 clears the interrupt |
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| Read accesses always return 0 |
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7 | Reset signal for DPLL | 02 | r/w |
| 0: Reset asserted |
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| 1: Normal operation |
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Reference Clock Source Register
Table 30: Reference Clock Source Register
Bit | Description | Default | Access |
1..0 | Selects clock source for reference clock | 002 | r/w |
| 002: RCVD_CLK_0 |
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| 012: RCVD_CLK_1 |
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| 102: RCVD_CLK_2 |
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| 112: RCVD_CLK_3 |
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3..2 | Selects interrupt rate for interrupt | 002 | r/w |
| LCCB_INT_N clocked by 2 kHz system |
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| clock reference |
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002: 500 µs
012: 1 ms
102: 10 ms
112: 1 s
PENT/ATCA−717 | 145 |
