Maps and Registers | FPGA Registers |
|
|
Table 35: Version Register
Bit | Description | Default | Access |
7..0 | FPGA version | FD16a(at the time of | r |
|
| writing this guide) |
|
Access Control Register
This register determines the current owner of the following interfaces:
SClock synchronisation building block interface
SEthernet switch management interface
SSPROM update interface
The current owner of each interface is either the IPMC or the host CPU.a
Only the current owner has write access to the corresponding registers. The non−proprietor has only read access.a
If the non−proprietor wants to become owner, it has to request ownership from the current owner. The current owner then has to grant ownership by inverting the bit corresponding to the interface.a
Table 36: Access Control Register
Bit | Description | Default | Access |
0 | Indicates the current owner of the clock | 02 | r/w |
| synchronisation building block interface |
|
|
| 0: Hosta |
|
|
| 1: IPMC |
|
|
1 | Indicates current owner of Ethernet switch | 12 | r/w |
| management interface |
|
|
| 0: Host |
|
|
| 1: IPMC |
|
|
2 | Indicates the current owner of the SPROM | 02 | r/w |
| update interface |
|
|
| 0: Host |
|
|
| 1: IPMC |
|
|
7..3 | Reserved | 000002 | r |
148 | PENT/ATCA−717 |
