Devices’ Features and Data Paths | South Bridge |
|
|
South Bridge
The used South Bridge is an Intel 6300ESB I/O controller hub device. It provides the interface between the Host Bridge and the legacy I/O. Integrated into the South Bridge are:aa
STwo 8237 DMA controllers
SOne 8254 counter timer
SInterrupt controller
SReal−time clock
SWatchdog
The interfaces provided by the South Bridge include:a
SHub interface 1.5
SPCI 2.2 interface
SPCI−X 1.0 interface
STwo parallel ATA interfaces
STwo serial ATA interfaces
STwo serial RS−232 interfaces
SFour USB interfaces
SLPC interface
SSMBus interface
Interrupt Controller
The interrupt controller residing in the South Bridge is 8259A−compliant and runs in PIC mode.a
The interrupts of the four PMC slots are merged and are routed through an FPGA to the interrupt controller where they are mapped to ISA compatible interrupts.a
The interrupt controller is also able to generate CPU Non−Maskable Interrupts (NMIs). Possible sources of NMIs are:aa
SMemory ECC and parity errors
108 | PENT/ATCA−717 |
