FPGA | Devices’ Features and Data Paths |
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FPGA
The FPGA implements the following functions:aaaaa
SLPC interface
SIPMC interface
SClock synchronization extensions
SReset controller
SInterrupt routing unit
SMiscellaneous glue logic
SEthernet switch interface
The FPGA loads its configuration stream from one of two EEPROMs which are connected to the FPGA. One EEPROM serves as default, the second as backup EEPROM. The IPMC controls which EEPROM the configuration stream is loaded from. After IPMC startup the FPGA loads its configuration stream from the default EEPROM. An IPMI System Boot Options command allows to select between default and backup EEPROM. For details about switching between default and backup FPGA refer to theaPENT/ATCA−715/717/7105/7107: Control via IPMI Programmer’s Guidea which can be downloaded from the Motorola literature site.aaa
LPC Interface
The LPC interface is compliant to the Intel LPC specification 1.1 and connects the FPGA to the South Bridge.a
IPMC Interface
The FPGA is connected to the on−board IPMC and implements the following IPMC related features:
STwo Block Transfer interfaces
SPort 80 register
SIPMC extensions
Block Transfer Interfaces
Two Block Transfer interfaces (BT) reside inside the FPGA. Each provides one control and status register, two 64−byte FIFOs and an interrupt mask register. Both BT interfaces are
PENT/ATCA−717 | 115 |
