Clock Synchronization Interface | Devices’ Features and Data Paths |
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S8 kHz frame clock/pulse with programmable pulse width and polarity (SYNC_0,1,2,3))
SAutomatic hit−less switch−over if one system clock fails
SActivity monitor for system clocks
SPhase build−out for output clock phase continuity during switch−over
SMeets jitter requirements up to OC−3 line rates
SProgrammable reference clock divider
The DPLL is clocked by an external oscillator running at 12.8 MHz. Two clock buffers provide a separate clock and synchronization signal for each of the four on−board PMC sites. The FPGA contains extensions which are related to the clock synchronization building block. Some of these extensions include registers that are accessible via the host and which allow to control and monitor the functionality of the clock synchronization building block. For details refer toasection "Clock Synchronization Interface Registers" on pagea144.a
PENT/ATCA−717 | 125 |
