Devices’ Features and Data Paths | Clock Synchronization Interface |
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Clock Synchronization Interface
AdvancedTCA systems provide a telecom clock synchronization interface which allows to synchronize elements within a telecommunication network. The telecom clock synchronization interface consists of three redundant clock buses (CLK1, CLK2 and CLK3) which are available at the system backplane. Each clock bus is implemented as a differential pair of MDS/LDS signals which connects to each system slot.aaa
In compliance with the AdvancedTCA PICMG 3.0 specification, CLK1 and CLK2 are used as system clocks and CLK3 is used as reference clock.a
The blade provides a clock synchronization building block which allows to synchronize the four on−board PMC modules to the system clock and to derive a reference clock. The main components of the clock synchronization building block as well as the main signal paths are shown in the following figure.aaa
PMC Slots
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| Oscillator |
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CLK_0 |
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| SYNC_B |
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CLK_1 | Clock |
| SYNC_A |
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CLK_2 |
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Buffer |
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CLK_3 |
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| NETREF_B |
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SYNC_0 |
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| SEC | SYS_CLK_B |
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SYNC_1 | Clock |
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| NETREF_A |
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SYNC_2 |
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Buffer |
| PRIM | SYS_CLK_A |
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SYNC_3 |
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RCVD_CLK_0 |
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RCVD_CLK_1 |
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RCVD_CLK_2 | FPGA |
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RCVD_CLK_3 |
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| A B A B A B | ||
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| CLK | 1 | 2 | 3 |
Figure 38: Clock Synchronization Building Block
The key component of the clock synchronization building block is the DPLL device ACS8525 from Semtech. Its main features include:
SSoftware programmable output clock synthesis (CLK_0, 1, 2, 3)
124 | PENT/ATCA−717 |
