Agilent Technologies 66lxxA manual Status Byte Register, Output Queue, Location Of Event Handles

Status Byte Register

This register summarizes the information from all other status groups as defined in the IEEE 488.2 Standard Digital Interface for Programmable Instrumentation standard. The bit configuration is shown in Table 4-2. The register can be read either by a serial poll or by *STB?. Both methods return the same data, except for bit 6. Sending *STB? returns MSS in bit 6, while polling returns RQS in bit 6.

The RQS Bit

Whenever the power module requests service, it sets the SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the controller services the interrupt, RQS is cleared inside the register and returned in bit position 6 of the response. The remaining bits of the Status Byte register are not disturbed.

The MSS Bit

This is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the Service Request Enable register. MSS is set whenever the power module has at least one reason (and possible more) for requesting service. Sending *STB? reads the MSS in bit position 6 of the response. No bits of the Status Byte register are cleared by reading it.

Determining the Cause of a Service Interrupt

You can determine the reason for an SRQ by the following actions:

∙Use a serial poll or the *STB? query to determine which summary bits are active.

∙Read the corresponding Event register for each summary bit to determine which events caused the summary bit to be set. When an Event register is read, it is cleared. This also clears the corresponding summary bit.

∙The interrupt will recur until the specific condition that caused the each event is removed. If this is not possible, the event may be disabled by programming the corresponding bit of the status group Enable register or NTRPTR filter. A faster way to prevent the interrupt is to disable the service request by programming the appropriate bit of the Service Request Enable register.

Output Queue

The Output Queue is a first-in, first-out (FIFO) data register that stores power module-to-controller messages until the controller reads them. Whenever the queue holds one or more bytes, it sets the MAV bit (4) of the Status Byte register. If too many unread error messages are accumulated in the queue, a system error message is generated (see "Chapter 6 - Error Messages"). The Output Queue is cleared at power on and by *CLS.

Location Of Event Handles

"Event handles" are signals within the interface that can be used for triggers, for a Trigger Out signal, or for a DFI signal. Those event handles derived from signals in the Status Subsystem are shown as circled numbers in Figure 4-1. Other event handles are described in "Chapter 5 - Synchronizing Power Module Output Changes".

54 Status Reporting