Status Registers

Use Status Registers to Determine the State of Analyzer Events and Conditions

Bit descriptions in the Questionable Status Power Condition Register are given in the following table.

Bit

Decimal

Description

 

Value

 

 

 

 

0

0

R.P.P Tripped: A 1 in this bit position indicates that the

 

 

reverse power protection is tripped (Agilent model E7401A

 

 

only). Reverse power protection is “overload” protection for

 

 

the tracking generator.

 

 

 

1

2

Source Unleveled: A 1 in this bit position indicates that

 

 

the source (tracking generator) output is unleveled.

 

 

 

2

4

Source LO Unleveled: A 1 in this bit position indicates

 

 

that the local oscillator (LO) in the source (tracking generator)

 

 

is unleveled.

 

 

 

3

8

LO Unleveled: A 1 in this bit position indicates that the

 

 

analyzer local oscillator (LO) is unleveled.

 

 

 

4

16

50 MHz Osc Unleveled: A 1 in this bit position indicates

 

 

that the 50 MHz amplitude reference signal is unleveled.

 

 

 

5

32

Reserved: This bit is not used by the analyzer, but is for

 

 

future use with other Agilent products.

 

 

 

6

64

Input Overload Tripped: A 1 in this bit position

 

 

indicates that the input overload protection is tripped (Agilent

 

 

EMC model E7401A only).

 

 

 

7

128

Unused: This bit is always set to 0.

 

 

 

8

256

LO Out Unleveled: A 1 in this bit position indicates that

 

 

the first local oscillator (LO) output is unleveled.

 

 

 

9

512

Unused: This bit is always set to 0.

 

 

 

10

1024

Unused: This bit is always set to 0.

 

 

 

11

2048

Unused: This bit is always set to 0.

 

 

 

12

4096

Unused: This bit is always set to 0.

 

 

 

13

8192

Unused: This bit is always set to 0.

 

 

 

14

16384

Unused: This bit is always set to 0.

 

 

 

15

32768

Always Zero (0): This bit is always set to 0.

 

 

 

Questionable Status Event Enable Register

The Questionable Status Event Enable Register lets you choose which bits in the Questionable Status Event Register will set the summary bit (bit 3 of the Status Byte Register) to 1. Send the command :STATus:QUEStionable:ENABle <num> where <num> is the sum of the decimal values of the bits you want to enable.

Chapter 2

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Agilent Technologies Model  A.08.xx manual Questionable Status Event Enable Register

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