AMD x86 Cycle 1-FETCH, Cycle 2-SCAN, Cycle 3 DirectPath, Cycle 3 VectorPath, Cycle 4 DirectPath

22007E/0 — November 1999 AMD Athlon™ Processor x86 Code Optimization

Cycle 1–FETCH	The FETCH pipeline stage calculates the address of the next
	x86 instruction window to fetch from the processor caches or
	system memory.
Cycle 2–SCAN	SCAN determines the start and end pointers of instructions.
	SCAN can send up to six aligned instructions (DirectPath and
	VectorPath) to ALIGN1 and only one VectorPath instruction to
	the microcode engine (MENG) per cycle.
Cycle 3 (DirectPath) –	Because each 8-byte buffer (quadword queue) can contain up to
ALIGN1	three instructions, ALIGN1 can buffer up to a maximum of nine
	instructions, or 24 instruction bytes. ALIGN1 tries to send three
	instructions from an 8-byte buffer to ALIGN2 per cycle.
Cycle 3 (VectorPath)–	For VectorPath instructions, the microcode engine control
MECTL	(MECTL) stage of the pipeline generates the microcode entry
	points.
Cycle 4 (DirectPath) –	ALIGN2 prioritizes prefix bytes, determines the opcode,
ALIGN2	ModR/M, and SIB bytes for each instruction and sends the
	accumulated prefix information to EDEC.
Cycle 4 (VectorPath)–	In the microcode engine ROM (MEROM) pipeline stage, the
MEROM	entry-point generated in the previous cycle, MECTL, is used to
	index into the MROM to obtain the microcode lines necessary
	to decode the instruction sent by SCAN.
Cycle 5 (DirectPath) –	The early decode (EDEC) stage decodes information from the
EDEC	DirectPath stage (ALIGN2) and VectorPath stage (MEROM)
	into MacroOPs. In addition, EDEC determines register
	pointers, flag updates, immediate values, displacements, and
	other information. EDEC then selects either MacroOPs from
	the DirectPath or MacroOPs from the VectorPath to send to the
	instruction decoder (IDEC) stage.
Cycle 5 (VectorPath)–	The microcode engine decode (MEDEC) stage converts x86
MEDEC/MESEQ	instructions into MacroOPs. The microcode engine sequencer
	(MESEQ) performs the sequence controls (redirects and
	exceptions) for the MENG.
Cycle 6–	At the instruction decoder (IDEC)/rename stage, integer and
IDEC/Rename	floating-point MacroOPs diverge in the pipeline. Integer
	MacroOPs are scheduled for execution in the next cycle.
	Floating-point MacroOPs have their floating-point stack

Fetch and Decode Pipeline Stages 143