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AMD x86 manual MTRRphysMaskn Register Format

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AMD Athlon™ Processor x86 Code Optimization

22007E/0 — November 1999

63

36

35

12

11

10

0

Physical Mask

V

Reserved

Symbol	Description	Bits
Physical Mask	24-Bit Mask	35–12

VVariable Range Register Pair Enabled 11 (V = 0 at reset)

Figure 17. MTRRphysMaskn Register Format

Note: A software attempt to write to reserved bits will generate a general protection exception.

Physical	Specifies a 24-bit mask to determine the range of
Mask	the region defined in the register pair.
V	Enables the register pair when set (V = 0 at reset).

Mask values can represent discontinuous ranges (when the mask defines a lower significant bit as zero and a higher significant bit as one). In a discontinuous range, the memory area not mapped by the mask value is set to the default type. Discontinuous ranges should not be used.

The range that is mapped by the variable-range MTRR register pair must meet the following range size and alignment rule:

■Each defined memory range must have a size equal to 2n (11 < n < 36).

■The base address for the address pair must be aligned to a similar 2n boundary.

An example of a variable MTRR pair is as follows:

To map the address range from 8 Mbytes (0080_0000h) to 16 Mbytes (00FF_FFFFh) as writeback memory, the base register should be loaded with 80_0006h, and the mask should be loaded with FFF8_00800h.

184	Page Attribute Table (PAT)

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AMD x86 manual MTRRphysMaskn Register Format

Contents

AMD AthlonTM Processor Trademarks Contents Instruction Decoding Optimizations Cache and Memory Optimizations Scheduling Optimizations Floating-Point Optimizations General x86 Optimization Guidelines 127 Appendix B Pipeline and Execution Unit Resources Overview Appendix E Programming the Mtrr and PAT List of Figures Xii List of Tables Xiv Revision History Xvi Introduction About this DocumentSource Level Optimizations. Describes optimizations that AMD Athlon Processor Family AMD Athlon Processor Microarchitecture Summary AMD Athlon Processor Microarchitecture Summary AMD Athlon Processor x86 Code Optimization Top Optimizations Memory Size and Alignment Issues Optimization StarGroup I Optimizations Essential Optimizations Use the 3DNow! Prefetch and Prefetchw InstructionsGroup II Optimizations-Secondary Optimizations Select DirectPath Over VectorPath InstructionsLoad-Execute Instruction Usage Use Load-Execute InstructionsAvoid Branches Dependent on Random Data Take Advantage of Write CombiningUse 3DNow! Instructions Avoid Placing Code and Data in the Same 64-Byte Cache Line 22007E/0 November Source Level Optimizations Use 32-Bit Data Types for Integer CodeExample Preferred Consider the Sign of Integer OperandsExample 1 Avoid Use Array Style Instead of Pointer Style Code Example AvoidUse unsigned types for Use signed types forVertex Example 2 Preferred Completely Unroll Small Loops Avoid Unnecessary Store-to-Load DependenciesAvoid Unnecessary Store-to-Load Dependencies Consider Expression Order in Compound Branch Conditions Use Prototypes for All Functions Switch Statement UsageOptimize Switch Statements Example Use Const Type QualifierGeneric Loop Hoisting Generalization for Multiple Constant Control Code Declare Local Functions as Static Dynamic Memory Allocation Consideration Introduce Explicit Parallelism into CodeExplicitly Extract Common Subexpressions Language Structure Component Considerations ExampleAvoid PreferredNew ordering, with padding Preferred Sort Local Variables According to Base Type SizeOriginal ordering Avoid Accelerating Floating-Point Divides and Square Roots Improved ordering PreferredAccelerating Floating-Point Divides and Square Roots Avoid Unnecessary Integer Division AMD Athlon Processor x86 Code Optimization Instruction Decoding Optimizations OverviewUse Load-Execute Integer Instructions Select DirectPath Over VectorPath InstructionsLoad-Execute Instruction Usage TOP Align Branch Targets in Program Hot Spots Use Short Instruction LengthsAvoid Partial Register Reads and Writes Example 2 AvoidUse 8-Bit Sign-Extended Immediates Replace Certain Shld Instructions with Alternative CodeUse 8-Bit Sign-Extended Displacements Code Padding Using Neutral Code FillersRecommendations for the AMD Athlon Processor Code Padding Using Neutral Code Fillers AMD Athlon Processor x86 Code Optimization NOP6EDI AMD Athlon Processor x86 Code Optimization Avoid Memory Size Mismatches Memory Size and Alignment IssuesCache and Memory Optimizations Align Data Where Possible Use the 3DNow! Prefetch and Prefetchw InstructionsExample Multiple Prefetches CodeMOV ECX, -LARGENUM Determining Prefetch Distance Prefetch Distance = 200 DS/C bytesTake Advantage of Write Combining Avoid Placing Code and Data in the Same 64-Byte Cache LineStore-to-Load Forwarding Restrictions Store-to-Load Forwarding Pitfalls -True DependenciesExample 3 Avoid Example 4 AvoidExample 7 Avoid Example 5 PreferredExample 6 Avoid Stack Alignment Considerations Summary of Store-to-Load Forwarding Pitfalls to AvoidAlign Tbyte Variables on Quadword Aligned Addresses Sort Variables According to Base Type Size Branch Optimizations Avoid Branches Dependent on Random DataAMD Athlon Processor Specific Code Blended AMD-K6and AMD Athlon Processor CodeExample 7 Integer Signum Function Always Pair Call and ReturnExample 6 Increment Ring Buffer Offset Replace Branches with Computation in 3DNow! Code Muxing Constructs3DNow! code Sample Code Translated into 3DNow! CodeCode MM5 Pfsub Psrad Avoid the Loop Instruction Avoid Far Control Transfer InstructionsAvoid Recursive Functions Scheduling Optimizations Schedule Instructions According to their LatencyUnrolling Loops Complete Loop UnrollingPartial Loop Unrolling Without Loop Unrolling With Partial Loop UnrollingDeriving Loop Control For PartiallyUnrolled Loops Example 1 rolled loopUse Function Inlining OverviewAvoid Address Generation Interlocks Always Inline Functions if Called from One SiteUse Movzx and Movsx Minimize Pointer Arithmetic in LoopsMOV ECX, Maxsize Push Memory Data Carefully Example 3 PreferredPush Memory Data Carefully Multiplication by Reciprocal Division Utility Integer OptimizationsReplace Divides with Multiplies Unsigned Division by Multiplication of Constant Restricted Dividend Signed Division by Multiplication of ConstantSimpler Code for Signed Division By Signed Division By 2nRemainder of Signed Integer 2 orUse Alternative Code When Multiplying by a Constant Integer 2n or -2nADD REG1, REG1 REG1, REG2 SHL Use MMX Instructions for Integer-Only Work Guidelines for Repeated String Instructions Repeated String Instruction UsageLatency of Repeated String Instructions Using Movq Ensure DF=0 UPAlign Source Destination withUse XOR Instruction to Clear Integer Registers Efficient 64-Bit Integer ArithmeticExample 6 Multiplication Example 4 Left shiftExample 5 Right shift Example 7 Division EBX, ESP+12 DividendloExample 8 Remainder SHR EDX Efficient Implementation of Population Count Function StepBit field. Thus the following computation is performed MOV EDX, EDX SHR Derivation of Multiplier Used for Integer Division by Utility sdiv.exe was compiled using the following code MOV ECX EDX Imul ADD SHR SAR Use Multiplies Rather than Divides Floating-Point OptimizationsEnsure All FPU Data is Aligned Floating-Point Compare Instructions Use Ffreep Macro to Pop One Register from the FPU StackAvoid Using Extended-Precision Data Use the Fxch Instruction Rather than FST/FLD PairsMinimize Floating-Point-to-Integer Conversions Example 1 FastExample 2 Potentially faster Example 3 Potentially faster Example 4 FastestFloating-Point Subexpression Elimination 104 Take Advantage of the Fsincos Instruction 106 Use Femms Instruction 3DNow! and MMX OptimizationsUse 3DNow! Instructions Optimized Full 24-Bit Precision Divide Use 3DNow! Instructions for Fast DivisionOptimized 14-Bit Precision Divide Pipelined Pair of 24-Bit Precision Divides Newton-Raphson ReciprocalOptimized 15-Bit Precision Square Root Optimized 24-Bit Precision Square RootNewton-Raphson Reciprocal Square Root 3DNow! and MMX Intra-Operand Swapping AMD AthlonSpecific Code Blended CodeFast Conversion of Signed Words to Floating-Point Use MMX Pxor to Negate 3DNow! DataUse MMX Pcmp Instead of 3DNow! Pfcmp Both NumbersPositive One Negative, One PositiveUse MMX Instructions for Block Copies and Block Fills AMD-K6and AMD Athlon Processor Blended Code116 Processor Specific Use MMX Pxor to Clear All Bits in an MMX Register Optimized Matrix Multiplication Use MMX Pcmpeqd to Set All Bits in an MMX RegisterMOV EBX, RES Optimized Matrix Multiplication 121 Data Use 3DNow! Pavgusb for MPEG-2 Motion Compensation MM0=QWORD1 Stream of Packed Unsigned Bytes Complex Number Arithmetic General x86 Optimization Guidelines Short FormsStack Allocation DependenciesRegister Operands AMD Athlon Processor Microarchitecture IntroductionAMD Athlon Processor Microarchitecture Superscalar ProcessorAMD Athlon Processor Microarchitecture 131 Predecode Branch PredictionEarly Decoding Instruction Control Unit Data CacheInteger Scheduler Integer Execution UnitFloating-Point Scheduler Floating-Point Execution Unit 12 toLoad-Store Unit LSU Load/Store UnitAMD Athlon System Bus L2 Cache ControllerWrite Combining 140 AMD Athlon Processor Microarchitecture Pipeline and Execution Unit Resources Overview Fetch and Decode Pipeline StagesC T L R O M Cycle 1-FETCH Cycle 2-SCANCycle 3 DirectPath Cycle 3 VectorPathInteger Pipeline Stages Integer Pipeline StagesCycle 7-SCHED Cycle 8-EXECCycle 9-ADDGEN Cycle 10 -DCACCFloating-Point Pipeline Stages Floating-Point Pipeline StagesCycle 7-STKREN Cycle 8-REGRENCycle 9-SCHEDW Cycle 10 -SCHEDExecution Unit Resources TerminologyOperands ResultsInteger Decode Types Integer Pipeline OperationsInteger Pipeline Operation Types Floating-Point Decode Types Floating-Point Pipeline OperationsFloating-Point Pipeline Operation Types Stage 1 Cycle Stage 2 Cycle Stage 3 Cycle Load/Store Pipeline OperationsLoad/Store Unit Stages Code Sample Analysis INC EBX ADD ESI, EDX Imul EAX, ECX INC ESI MOVADD EDI, EBX SHL SAR Sample 2 Integer Register and Memory Load OperationsDEC EDX MOV EDI, ECX SUB Appendix C Implementation Write CombiningProgramming Details What is Write Combining?Write-Combining Definitions and Abbreviations Write-Combining Operations Write Combining Completion Events INIT, HaltAMD Athlon System Bus Commands Generation Rules Sending Write-Buffer Data to the System160 Write-Combining Operations Performance-Monitoring Counters Performance Counter UsagePerfEvtSel30 MSRs MSR Addresses C0010000h-C0010003h PerfEvtSel30 RegistersPerformance Counter Usage 163 Performance-Monitoring Counters 65h 73hSnoop hits 74hEvent Source Event Description Waited to use the L2Instruction cache fetches Instruction cache missesPerfCtr30 MSRs MSR Addresses C0010004h-C0010007h Event and Time-Stamp Monitoring Software Starting and Stopping the Performance-Monitoring CountersMonitoring Counter Overflow 170 Monitoring Counter Overflow Programming the Mtrr Memory Type Range Register Mtrr Mechanism172 Memory Type Range Register Mtrr Mechanism 100000h Kbytes each Fixed Ranges C0000h 80000h Fixed RangesFFFFFFFFh Memory Types Memory Type EncodingsMtrr Capability Register FormatMemory Type Range Register Mtrr Mechanism 175 Standard Mtrr Types and Properties Attribute Table PAT Attribute Table MSR 277hPAT Entry Reset Value PATi 3-Bit EncodingsMTRRs and PAT PATiEffective Memory Type Based on PAT and MTRRs PAT Memory Type Mtrr Memory TypeFinal Output Memory Types Input Memory TypeAttribute Table PAT 181 7FFFF 6FFFF 5FFFF 4FFFF 3FFFF 2FFFF 1FFFF 0FFFF 9FFFF 9BFFF 97FFF 93FFF 8FFFF 8BFFF 87FFF 83FFFBffff Bbfff B7FFF B3FFF Affff Abfff A7FFF A3FFF C7FFF C6FFF C5FFF C4FFF C3FFF C2FFF C1FFF C0FFFAttribute Table PAT 183 MTRRphysMaskn Register Format MTRR-Related Model-Specific Register MSR Map 186 Appendix F Instruction Dispatch Execution ResourcesInteger Instructions AAAAAD AAMModR/M Decode Byte ADC mreg8, reg8ADC mem8, reg8 ADC mreg16/32, reg16/32Bound Bswap EAXBswap ECX Bswap EDXCBW/CWDE CLCCLD CLICMOVE/CMOVZ reg16/32, reg16/32 0Fh CMOVE/CMOVZ reg16/32, mem16/32 0FhCMOVG/CMOVNLE reg16/32, reg16/32 0Fh CMOVG/CMOVNLE reg16/32, mem16/32 0FhCpuid CWD/CDQDAA DASEnter AL, DXAX, DX EAX, DXInvd InvlpgLahf LeaveLOOPE/LOOPZ disp8 E1h LOOPNE/LOOPNZ disp8 E0hLSL reg16/32, mreg16/32 0Fh 03h LSL reg16/32, mem16/32 0Fh 03hNOP Xchg EAX, EAX OUT DX, AL OUT DX, AXOUT DX, EAX POP ESPOP EBX POP ESPPOP EBP POP ESIRdtsc RdmsrRdpmc Sahf SBB mreg16/32, reg16/32 SBB mem16/32, reg16/32SBB reg8, mreg8 SBB reg8, mem8Sets mreg8 Sets mem8Setns mreg8 Setns mem8STI STCSTD Syscall SysenterSysexit SysretXchg EAX, EAX Xchg EAX, ECXXchg EAX, EDX Xchg EAX, EBXMMX Instructions EmmsPandn mmreg1, mmreg2 DFhPandn mmreg, mem64 Pcmpeqb mmreg1, mmreg2FADD/FMUL MMX Extensions FPUFloating-Point Instructions Fdecstp FcomppFcos FLD1 FincstpFinit FLDL2E FLDL2TFLDLG2 FLDLN2Fstsw AX FtstFucom FucompDNow! Instructions FemmsDNow! Extensions DirectPath versus VectorPath Instructions DirectPath InstructionsCBW/CWDE CLC CMC DirectPath Integer InstructionsBT mreg16/32, reg16/32 BT mreg16/32, imm8 BT mem16/32, imm8 DEC mreg8 DEC mem8 DEC mreg16/32 DEC mem16/32 INC mreg8 INC mem8 INC mreg16/32 INC mem16/32 JO short disp8222 DirectPath Instructions DirectPath Instructions 223 224 DirectPath Instructions Wait Xchg EAX, EAX 226 DirectPath Instructions DirectPath MMX Instructions DirectPath MMX Extensions DirectPath Floating-Point Instructions Fcompp FdecstpFist mem16int FLD1 FLDL2E FLDL2T FLDLG2 FLDLN2 Fldpi FldzFtst Fucom Fucomp Fucompp Fwait Fxch VectorPath Instructions VectorPath Integer InstructionsAAA AAD AAM AAS CLD CLI CltsInstruction Mnemonic DIV EAX, mem16/32 AL, DX AX, DX EAX, DX Invd InvlpgPOP mreg 16/32 POP mem 16/32 Push mreg16/32 Push mem16/32PUSHA/PUSHAD PUSHF/PUSHFD Rdmsr Rdpmc RdtscVectorPath MMX Instructions VectorPath MMX ExtensionsSyscall Sysenter Sysexit Sysret Wbinvd WrmsrVectorPath Floating-Point Instructions Fptan Fpatan FrndintFscale Fsin Fsincos Fxam Fxtract FYL2X FYL2XP1236 Index 238 Index Index 239 240 Index